6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-25 16:30:05 +00:00
Code Issues Projects Releases Wiki Activity

When using CR bit registers on PPC32, handle the i1 vaarg case

Browse Source 
When copying an i1 value into a GPR for a vaarg call, we need to explicitly
zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be
generated).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203041 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2014-03-06 00:23:33 +00:00
parent 7cf9764966
commit 025c1cefca
2 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -3773,6 +3773,9 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
}
if (VA.isRegLoc()) {
if (Arg.getValueType() == MVT::i1)
Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
seenFloatArg |= VA.getLocVT().isFloatingPoint();
// Put argument in a physical register.
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));

15
test/CodeGen/PowerPC/ppc32-i1-vaarg.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc < %s -march=ppc32 -mcpu=ppc32 | FileCheck %s
target triple = "powerpc-unknown-linux-gnu"
declare void @printf(i8*, ...)
define void @main() {
call void (i8*, ...)* @printf(i8* undef, i1 false)
ret void
}
; CHECK-LABEL: @main
; CHECK-DAG li 4, 0
; CHECK-DAG: crxor 6, 6, 6
; CHECK: bl printf