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Switched to using BitsToDouble for int_to_float to avoid aliasing problem.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22831 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2005-08-17 17:42:52 +00:00
parent 59b8fcfa5f
commit 02659d2363
1 changed files with 4 additions and 4 deletions
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8
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -15,6 +15,7 @@
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetOptions.h"
@ -204,10 +205,9 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
DAG.getSrcValue(NULL));
// FP constant to bias correct the final result
uint64_t SignedBias = 0x4330000080000000ULL;
uint64_t UnsignedBias = 0x4330000000000000ULL;
SDOperand Bias = DAG.getConstantFP(isSigned ? *(double *)&SignedBias
: *(double *)&UnsignedBias,
SDOperand Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL)
: BitsToDouble(0x4330000000000000ULL),
MVT::f64);
// subtract the bias
SDOperand Sub = DAG.getNode(ISD::SUB, MVT::f64, Load, Bias);