mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195408 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jiangning Liu
parent
ca3c03a167
commit
0282fe6d91
@ -1592,29 +1592,29 @@ def Neon_High4S : PatFrag<(ops node:$in),
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(extract_subvector (v4i32 node:$in), (iPTR 2))>;
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def Neon_High2D : PatFrag<(ops node:$in),
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(extract_subvector (v2i64 node:$in), (iPTR 1))>;
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def Neon_High4f : PatFrag<(ops node:$in),
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(extract_subvector (v4f32 node:$in), (iPTR 2))>;
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def Neon_High2d : PatFrag<(ops node:$in),
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(extract_subvector (v2f64 node:$in), (iPTR 1))>;
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def Neon_High4float : PatFrag<(ops node:$in),
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(extract_subvector (v4f32 node:$in), (iPTR 2))>;
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def Neon_High2double : PatFrag<(ops node:$in),
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(extract_subvector (v2f64 node:$in), (iPTR 1))>;
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def Neon_low16B : PatFrag<(ops node:$in),
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def Neon_Low16B : PatFrag<(ops node:$in),
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(v8i8 (extract_subvector (v16i8 node:$in),
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(iPTR 0)))>;
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def Neon_low8H : PatFrag<(ops node:$in),
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def Neon_Low8H : PatFrag<(ops node:$in),
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(v4i16 (extract_subvector (v8i16 node:$in),
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(iPTR 0)))>;
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def Neon_low4S : PatFrag<(ops node:$in),
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def Neon_Low4S : PatFrag<(ops node:$in),
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(v2i32 (extract_subvector (v4i32 node:$in),
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(iPTR 0)))>;
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def Neon_low2D : PatFrag<(ops node:$in),
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def Neon_Low2D : PatFrag<(ops node:$in),
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(v1i64 (extract_subvector (v2i64 node:$in),
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(iPTR 0)))>;
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def Neon_low4f : PatFrag<(ops node:$in),
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(v2f32 (extract_subvector (v4f32 node:$in),
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(iPTR 0)))>;
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def Neon_low2d : PatFrag<(ops node:$in),
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(v1f64 (extract_subvector (v2f64 node:$in),
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(iPTR 0)))>;
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def Neon_Low4float : PatFrag<(ops node:$in),
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(v2f32 (extract_subvector (v4f32 node:$in),
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(iPTR 0)))>;
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def Neon_Low2double : PatFrag<(ops node:$in),
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(v1f64 (extract_subvector (v2f64 node:$in),
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(iPTR 0)))>;
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def neon_uimm3_shift : Operand<i32>,
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ImmLeaf<i32, [{return Imm < 8;}]> {
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@ -5871,17 +5871,17 @@ multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
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multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh,
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ValueType ResTy, ValueType OpTy> {
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def : Pat<(ResTy (GetLow VPR128:$Rn)),
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(ResTy (DUPdv_D (OpTy VPR128:$Rn), 0))>;
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(ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
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def : Pat<(ResTy (GetHigh VPR128:$Rn)),
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(ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
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}
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defm : NeonI_SDUP<Neon_low16B, Neon_High16B, v8i8, v16i8>;
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defm : NeonI_SDUP<Neon_low8H, Neon_High8H, v4i16, v8i16>;
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defm : NeonI_SDUP<Neon_low4S, Neon_High4S, v2i32, v4i32>;
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defm : NeonI_SDUP<Neon_low2D, Neon_High2D, v1i64, v2i64>;
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defm : NeonI_SDUP<Neon_low4f, Neon_High4f, v2f32, v4f32>;
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defm : NeonI_SDUP<Neon_low2d, Neon_High2d, v1f64, v2f64>;
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defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
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defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
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defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
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defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
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defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
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defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
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// Patterns for vector extract of FP data using scalar DUP instructions
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defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
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@ -6232,7 +6232,7 @@ multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
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op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
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op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
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@ -6241,7 +6241,7 @@ multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
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op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
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op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
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@ -6349,7 +6349,7 @@ multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
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op, VPR64, VPR128, v2i32, v2i32, v4i32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
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op, VPR128, VPR128, v4i32, v4i32, v4i32,
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@ -6358,7 +6358,7 @@ multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
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op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
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op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
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@ -6435,7 +6435,7 @@ multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
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op, VPR64, VPR128, v2f32, v2f32, v4f32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4f node:$LHS), node:$RHS)>>;
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(Neon_Low4float node:$LHS), node:$RHS)>>;
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
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op, VPR128, VPR128, v4f32, v4f32, v4f32,
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@ -6532,7 +6532,7 @@ multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
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def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
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neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4f node:$LHS), node:$RHS)>>;
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(Neon_Low4float node:$LHS), node:$RHS)>>;
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def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
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neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
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@ -6566,12 +6566,12 @@ multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
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def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
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neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
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BinOpFrag<(fneg (Neon_vduplane
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(Neon_low4f node:$LHS), node:$RHS))>>;
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(Neon_Low4float node:$LHS), node:$RHS))>>;
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def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
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neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4f (fneg node:$LHS)),
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(Neon_Low4float (fneg node:$LHS)),
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node:$RHS)>>;
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def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
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@ -6739,22 +6739,22 @@ multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
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op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
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op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
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op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
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op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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// Index can only be half of the max value for lane in 64-bit vector
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@ -6805,23 +6805,23 @@ multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
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op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
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op, VPR64, VPR128, v2i64, v2i32, v4i32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
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op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
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Neon_High8H,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
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op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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// Index can only be half of the max value for lane in 64-bit vector
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@ -6864,25 +6864,25 @@ multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
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!cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
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v4i32, v4i16, v8i16,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
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!cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
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v2i64, v2i32, v4i32,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
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!cast<PatFrag>(op # "_4s"), VPR128Lo,
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v4i32, v8i16, v8i16, v4i16, Neon_High8H,
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BinOpFrag<(Neon_vduplane
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(Neon_low8H node:$LHS), node:$RHS)>>;
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(Neon_Low8H node:$LHS), node:$RHS)>>;
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def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
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!cast<PatFrag>(op # "_2d"), VPR128,
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v2i64, v4i32, v4i32, v2i32, Neon_High4S,
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BinOpFrag<(Neon_vduplane
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(Neon_low4S node:$LHS), node:$RHS)>>;
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(Neon_Low4S node:$LHS), node:$RHS)>>;
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// Index can only be half of the max value for lane in 64-bit vector
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@ -1,7 +1,7 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @test_vget_high_s8(<16 x i8> %a) {
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; CHECK: test_vget_high_s8:
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; CHECK-LABEL: test_vget_high_s8:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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@ -9,7 +9,7 @@ entry:
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}
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define <4 x i16> @test_vget_high_s16(<8 x i16> %a) {
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; CHECK: test_vget_high_s16:
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; CHECK-LABEL: test_vget_high_s16:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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@ -17,7 +17,7 @@ entry:
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}
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define <2 x i32> @test_vget_high_s32(<4 x i32> %a) {
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; CHECK: test_vget_high_s32:
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; CHECK-LABEL: test_vget_high_s32:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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@ -25,7 +25,7 @@ entry:
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}
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define <1 x i64> @test_vget_high_s64(<2 x i64> %a) {
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; CHECK: test_vget_high_s64:
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; CHECK-LABEL: test_vget_high_s64:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
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@ -33,7 +33,7 @@ entry:
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}
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define <8 x i8> @test_vget_high_u8(<16 x i8> %a) {
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; CHECK: test_vget_high_u8:
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; CHECK-LABEL: test_vget_high_u8:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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@ -41,7 +41,7 @@ entry:
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}
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define <4 x i16> @test_vget_high_u16(<8 x i16> %a) {
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; CHECK: test_vget_high_u16:
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; CHECK-LABEL: test_vget_high_u16:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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@ -49,7 +49,7 @@ entry:
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}
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define <2 x i32> @test_vget_high_u32(<4 x i32> %a) {
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; CHECK: test_vget_high_u32:
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; CHECK-LABEL: test_vget_high_u32:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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@ -57,7 +57,7 @@ entry:
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}
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define <1 x i64> @test_vget_high_u64(<2 x i64> %a) {
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; CHECK: test_vget_high_u64:
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; CHECK-LABEL: test_vget_high_u64:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
|
||||
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
|
||||
@ -65,7 +65,7 @@ entry:
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vget_high_p64(<2 x i64> %a) {
|
||||
; CHECK: test_vget_high_p64:
|
||||
; CHECK-LABEL: test_vget_high_p64:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[1]
|
||||
entry:
|
||||
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
|
||||
@ -73,7 +73,7 @@ entry:
|
||||
}
|
||||
|
||||
define <4 x i16> @test_vget_high_f16(<8 x i16> %a) {
|
||||
; CHECK: test_vget_high_f16:
|
||||
; CHECK-LABEL: test_vget_high_f16:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[1]
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
@ -81,7 +81,7 @@ entry:
|
||||
}
|
||||
|
||||
define <2 x float> @test_vget_high_f32(<4 x float> %a) {
|
||||
; CHECK: test_vget_high_f32:
|
||||
; CHECK-LABEL: test_vget_high_f32:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[1]
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 2, i32 3>
|
||||
@ -89,7 +89,7 @@ entry:
|
||||
}
|
||||
|
||||
define <8 x i8> @test_vget_high_p8(<16 x i8> %a) {
|
||||
; CHECK: test_vget_high_p8:
|
||||
; CHECK-LABEL: test_vget_high_p8:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[1]
|
||||
entry:
|
||||
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
@ -97,7 +97,7 @@ entry:
|
||||
}
|
||||
|
||||
define <4 x i16> @test_vget_high_p16(<8 x i16> %a) {
|
||||
; CHECK: test_vget_high_p16:
|
||||
; CHECK-LABEL: test_vget_high_p16:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[1]
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
@ -105,7 +105,7 @@ entry:
|
||||
}
|
||||
|
||||
define <1 x double> @test_vget_high_f64(<2 x double> %a) {
|
||||
; CHECK: test_vget_high_f64:
|
||||
; CHECK-LABEL: test_vget_high_f64:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[1]
|
||||
entry:
|
||||
%shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> <i32 1>
|
||||
@ -113,112 +113,112 @@ entry:
|
||||
}
|
||||
|
||||
define <8 x i8> @test_vget_low_s8(<16 x i8> %a) {
|
||||
; CHECK: test_vget_low_s8:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_s8:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i8> %shuffle.i
|
||||
}
|
||||
|
||||
define <4 x i16> @test_vget_low_s16(<8 x i16> %a) {
|
||||
; CHECK: test_vget_low_s16:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_s16:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
ret <4 x i16> %shuffle.i
|
||||
}
|
||||
|
||||
define <2 x i32> @test_vget_low_s32(<4 x i32> %a) {
|
||||
; CHECK: test_vget_low_s32:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_s32:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
|
||||
ret <2 x i32> %shuffle.i
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vget_low_s64(<2 x i64> %a) {
|
||||
; CHECK: test_vget_low_s64:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_s64:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer
|
||||
ret <1 x i64> %shuffle.i
|
||||
}
|
||||
|
||||
define <8 x i8> @test_vget_low_u8(<16 x i8> %a) {
|
||||
; CHECK: test_vget_low_u8:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_u8:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i8> %shuffle.i
|
||||
}
|
||||
|
||||
define <4 x i16> @test_vget_low_u16(<8 x i16> %a) {
|
||||
; CHECK: test_vget_low_u16:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_u16:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
ret <4 x i16> %shuffle.i
|
||||
}
|
||||
|
||||
define <2 x i32> @test_vget_low_u32(<4 x i32> %a) {
|
||||
; CHECK: test_vget_low_u32:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_u32:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
|
||||
ret <2 x i32> %shuffle.i
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vget_low_u64(<2 x i64> %a) {
|
||||
; CHECK: test_vget_low_u64:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_u64:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer
|
||||
ret <1 x i64> %shuffle.i
|
||||
}
|
||||
|
||||
define <1 x i64> @test_vget_low_p64(<2 x i64> %a) {
|
||||
; CHECK: test_vget_low_p64:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_p64:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer
|
||||
ret <1 x i64> %shuffle.i
|
||||
}
|
||||
|
||||
define <4 x i16> @test_vget_low_f16(<8 x i16> %a) {
|
||||
; CHECK: test_vget_low_f16:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_f16:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
ret <4 x i16> %shuffle.i
|
||||
}
|
||||
|
||||
define <2 x float> @test_vget_low_f32(<4 x float> %a) {
|
||||
; CHECK: test_vget_low_f32:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_f32:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
|
||||
ret <2 x float> %shuffle.i
|
||||
}
|
||||
|
||||
define <8 x i8> @test_vget_low_p8(<16 x i8> %a) {
|
||||
; CHECK: test_vget_low_p8:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_p8:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i8> %shuffle.i
|
||||
}
|
||||
|
||||
define <4 x i16> @test_vget_low_p16(<8 x i16> %a) {
|
||||
; CHECK: test_vget_low_p16:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_p16:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
ret <4 x i16> %shuffle.i
|
||||
}
|
||||
|
||||
define <1 x double> @test_vget_low_f64(<2 x double> %a) {
|
||||
; CHECK: test_vget_low_f64:
|
||||
; CHECK: dup d0, {{v[0-9]+}}.d[0]
|
||||
; CHECK-LABEL: test_vget_low_f64:
|
||||
; CHECK: ret
|
||||
entry:
|
||||
%shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> zeroinitializer
|
||||
ret <1 x double> %shuffle.i
|
||||
|
||||
Loading…
Reference in New Issue
Block a user