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[Hexagon] Updating indexed load-extend patterns and changing test to new expected output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
0170a308ec
commit
02b677594c
@ -1558,44 +1558,32 @@ multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
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def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
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}
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def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)),
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(L2_loadrb_io AddrFI:$addr, 0) >;
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def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)),
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(L2_loadrub_io AddrFI:$addr, 0) >;
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def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
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(L2_loadrh_io AddrFI:$addr, 0) >;
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def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
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(L2_loadruh_io AddrFI:$addr, 0) >;
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def : Pat < (i32 (load ADDRriS11_2:$addr)),
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(L2_loadri_io AddrFI:$addr, 0) >;
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def : Pat < (i64 (load ADDRriS11_3:$addr)),
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(L2_loadrd_io AddrFI:$addr, 0) >;
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let AddedComplexity = 20 in {
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def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
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(L2_loadrb_io IntRegs:$src1, s11_0ExtPred:$offset) >;
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defm: Loadx_pat<load, i32, s11_2ExtPred, L2_loadri_io>;
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defm: Loadx_pat<load, i64, s11_3ExtPred, L2_loadrd_io>;
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defm: Loadx_pat<atomic_load_8 , i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<atomic_load_16, i32, s11_1ExtPred, L2_loadruh_io>;
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defm: Loadx_pat<atomic_load_32, i32, s11_2ExtPred, L2_loadri_io>;
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defm: Loadx_pat<atomic_load_64, i64, s11_3ExtPred, L2_loadrd_io>;
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def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))),
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(L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset) >;
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def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
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(L2_loadrh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
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def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
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(L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
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def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
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(L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset) >;
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def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),
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(L2_loadrd_io IntRegs:$src1, s11_3ExtPred:$offset) >;
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defm: Loadx_pat<extloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
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//defm: Loadx_pat<extloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<extloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
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//defm: Loadx_pat<sextloadi8, i32, s11_0ExtPred, L2_loadrb_io>;
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defm: Loadx_pat<sextloadi16, i32, s11_1ExtPred, L2_loadrh_io>;
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defm: Loadx_pat<zextloadi1, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<zextloadi8, i32, s11_0ExtPred, L2_loadrub_io>;
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defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
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// No sextloadi1.
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}
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// Sign-extending loads of i1 need to replicate the lowest bit throughout
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// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should
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// do the trick.
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let AddedComplexity = 20 in
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def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))),
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(SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>;
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//===----------------------------------------------------------------------===//
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// Post increment load
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//===----------------------------------------------------------------------===//
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@ -1,12 +1,12 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate load instruction with (base + register offset << 0)
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we generate load instruction with (base + register offset << x)
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; load word
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define i32 @load_w(i32* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
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entry:
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%tmp = shl i32 %n, 4
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%tmp = add i32 %n, %m
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%scevgep9 = getelementptr i32* %a, i32 %tmp
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%val = load i32* %scevgep9, align 4
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ret i32 %val
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@ -14,10 +14,10 @@ entry:
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; load unsigned half word
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define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
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entry:
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%tmp = shl i32 %n, 4
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%tmp = add i32 %n, %m
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%scevgep9 = getelementptr i16* %a, i32 %tmp
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%val = load i16* %scevgep9, align 2
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ret i16 %val
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@ -25,10 +25,10 @@ entry:
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; load signed half word
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define i32 @load_h(i16* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
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entry:
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%tmp = shl i32 %n, 4
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%tmp = add i32 %n, %m
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%scevgep9 = getelementptr i16* %a, i32 %tmp
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%val = load i16* %scevgep9, align 2
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%conv = sext i16 %val to i32
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@ -37,10 +37,10 @@ entry:
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; load unsigned byte
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define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
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entry:
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%tmp = shl i32 %n, 4
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%tmp = add i32 %n, %m
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%scevgep9 = getelementptr i8* %a, i32 %tmp
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%val = load i8* %scevgep9, align 1
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ret i8 %val
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@ -48,10 +48,10 @@ entry:
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; load signed byte
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define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
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entry:
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%tmp = shl i32 %n, 4
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%tmp = add i32 %n, %m
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%scevgep9 = getelementptr i8* %a, i32 %tmp
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%val = load i8* %scevgep9, align 1
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%conv = sext i8 %val to i32
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@ -60,10 +60,10 @@ entry:
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; load doubleword
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define i64 @load_d(i64* nocapture %a, i32 %n) nounwind {
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; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0)
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define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
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; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
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entry:
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%tmp = shl i32 %n, 4
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%tmp = add i32 %n, %m
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%scevgep9 = getelementptr i64* %a, i32 %tmp
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%val = load i64* %scevgep9, align 8
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ret i64 %val
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