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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-13 07:31:28 +00:00
Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of
argument passing. Consolidate all SingletonRegister detection and handling into a new InstructionInfo::getSingletonRegisterForToken method instead of having it scattered about. No change in generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
4d43d0fd99
commit
02bcbc97fb
@ -228,7 +228,7 @@ static bool IsAssemblerInstruction(StringRef Name,
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}
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namespace {
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class AsmMatcherInfo;
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struct SubtargetFeatureInfo;
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/// ClassInfo - Helper class for storing the information about a particular
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@ -411,6 +411,11 @@ struct InstructionInfo {
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/// ConvertToMCInst to convert parsed operands into an MCInst for this
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/// function.
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std::string ConversionFnKind;
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/// getSingletonRegisterForToken - If the specified token is a singleton
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/// register, return the register name, otherwise return a null StringRef.
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StringRef getSingletonRegisterForToken(unsigned i,
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const AsmMatcherInfo &Info) const;
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/// operator< - Compare two instructions.
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bool operator<(const InstructionInfo &RHS) const {
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@ -493,6 +498,9 @@ public:
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/// The tablegen AsmParser record.
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Record *AsmParser;
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/// Target - The target information.
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CodeGenTarget &Target;
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/// The AsmParser "CommentDelimiter" value.
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std::string CommentDelimiter;
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@ -531,18 +539,17 @@ private:
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/// BuildRegisterClasses - Build the ClassInfo* instances for register
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/// classes.
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void BuildRegisterClasses(CodeGenTarget &Target,
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std::set<std::string> &SingletonRegisterNames);
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void BuildRegisterClasses(std::set<std::string> &SingletonRegisterNames);
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/// BuildOperandClasses - Build the ClassInfo* instances for user defined
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/// operand classes.
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void BuildOperandClasses(CodeGenTarget &Target);
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void BuildOperandClasses();
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public:
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AsmMatcherInfo(Record *_AsmParser);
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AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target);
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/// BuildInfo - Construct the various tables used during matching.
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void BuildInfo(CodeGenTarget &Target);
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void BuildInfo();
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/// getSubtargetFeature - Lookup or create the subtarget feature info for the
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/// given operand.
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@ -585,6 +592,43 @@ void InstructionInfo::dump() {
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}
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}
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/// getRegisterRecord - Get the register record for \arg name, or 0.
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static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
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for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
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const CodeGenRegister &Reg = Target.getRegisters()[i];
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if (Name == Reg.TheDef->getValueAsString("AsmName"))
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return Reg.TheDef;
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}
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return 0;
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}
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/// getSingletonRegisterForToken - If the specified token is a singleton
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/// register, return the register name, otherwise return a null StringRef.
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StringRef InstructionInfo::
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getSingletonRegisterForToken(unsigned i, const AsmMatcherInfo &Info) const {
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StringRef Tok = Tokens[i];
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if (!Tok.startswith(Info.RegisterPrefix))
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return StringRef();
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StringRef RegName = Tok.substr(Info.RegisterPrefix.size());
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Record *Rec = getRegisterRecord(Info.Target, RegName);
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if (!Rec) {
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// If there is no register prefix (i.e. "%" in "%eax"), then this may
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// be some random non-register token, just ignore it.
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if (Info.RegisterPrefix.empty())
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return StringRef();
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std::string Err = "unable to find register for '" + RegName.str() +
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"' (which matches register prefix)";
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throw TGError(Instr->TheDef->getLoc(), Err);
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}
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return RegName;
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}
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static std::string getEnumNameForToken(StringRef Str) {
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std::string Res;
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@ -604,17 +648,6 @@ static std::string getEnumNameForToken(StringRef Str) {
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return Res;
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}
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/// getRegisterRecord - Get the register record for \arg name, or 0.
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static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
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for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
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const CodeGenRegister &Reg = Target.getRegisters()[i];
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if (Name == Reg.TheDef->getValueAsString("AsmName"))
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return Reg.TheDef;
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}
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return 0;
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}
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ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
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ClassInfo *&Entry = TokenClasses[Token];
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@ -658,8 +691,7 @@ AsmMatcherInfo::getOperandClass(StringRef Token,
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return CI;
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}
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void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
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std::set<std::string>
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void AsmMatcherInfo::BuildRegisterClasses(std::set<std::string>
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&SingletonRegisterNames) {
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std::vector<CodeGenRegisterClass> RegisterClasses;
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std::vector<CodeGenRegister> Registers;
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@ -781,7 +813,7 @@ void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
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}
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}
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void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
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void AsmMatcherInfo::BuildOperandClasses() {
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std::vector<Record*> AsmOperands;
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AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
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@ -839,14 +871,14 @@ void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
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}
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}
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AsmMatcherInfo::AsmMatcherInfo(Record *asmParser)
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: AsmParser(asmParser),
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AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
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: AsmParser(asmParser), Target(target),
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CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
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RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
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{
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}
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void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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void AsmMatcherInfo::BuildInfo() {
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// Build information about all of the AssemblerPredicates.
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std::vector<Record*> AllPredicates =
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Records.getAllDerivedDefinitions("Predicate");
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@ -869,10 +901,9 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Parse the instructions; we need to do this first so that we can gather the
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// singleton register classes.
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std::set<std::string> SingletonRegisterNames;
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const std::vector<const CodeGenInstruction*> &InstrList =
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Target.getInstructionsByEnumValue();
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for (unsigned i = 0, e = InstrList.size(); i != e; ++i) {
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const CodeGenInstruction &CGI = *InstrList[i];
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I) {
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const CodeGenInstruction &CGI = **I;
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// If the tblgen -match-prefix option is specified (for tblgen hackers),
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// filter the set of instructions we consider.
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@ -903,24 +934,10 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Collect singleton registers, if used.
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for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
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if (!II->Tokens[i].startswith(RegisterPrefix))
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continue;
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StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
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Record *Rec = getRegisterRecord(Target, RegName);
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if (!Rec) {
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// If there is no register prefix (i.e. "%" in "%eax"), then this may
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// be some random non-register token, just ignore it.
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if (RegisterPrefix.empty())
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continue;
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std::string Err = "unable to find register for '" + RegName.str() +
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"' (which matches register prefix)";
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throw TGError(CGI.TheDef->getLoc(), Err);
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}
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SingletonRegisterNames.insert(RegName);
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StringRef RegName = II->getSingletonRegisterForToken(i, *this);
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if (RegName != StringRef())
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SingletonRegisterNames.insert(RegName);
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}
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// Compute the require features.
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@ -934,10 +951,10 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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}
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// Build info for the register classes.
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BuildRegisterClasses(Target, SingletonRegisterNames);
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BuildRegisterClasses(SingletonRegisterNames);
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// Build info for the user defined assembly operand classes.
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BuildOperandClasses(Target);
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BuildOperandClasses();
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// Build the instruction information.
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for (std::vector<InstructionInfo*>::iterator it = Instructions.begin(),
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@ -945,34 +962,29 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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InstructionInfo *II = *it;
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// The first token of the instruction is the mnemonic, which must be a
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// simple string.
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// simple string, not a $foo variable or a singleton register.
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assert(!II->Tokens.empty() && "Instruction has no tokens?");
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StringRef Mnemonic = II->Tokens[0];
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assert(Mnemonic[0] != '$' &&
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(RegisterPrefix.empty() || !Mnemonic.startswith(RegisterPrefix)));
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if (Mnemonic[0] == '$' ||
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II->getSingletonRegisterForToken(0, *this) != StringRef())
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throw TGError(II->Instr->TheDef->getLoc(),
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"Invalid instruction mnemonic '" + Mnemonic.str() + "'!");
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// Parse the tokens after the mnemonic.
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for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) {
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StringRef Token = II->Tokens[i];
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// Check for singleton registers.
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if (Token.startswith(RegisterPrefix)) {
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StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
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if (Record *RegRecord = getRegisterRecord(Target, RegName)) {
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InstructionInfo::Operand Op;
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Op.Class = RegisterClasses[RegRecord];
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Op.OperandInfo = 0;
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assert(Op.Class && Op.Class->Registers.size() == 1 &&
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"Unexpected class for singleton register");
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II->Operands.push_back(Op);
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continue;
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}
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if (!RegisterPrefix.empty()) {
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std::string Err = "unable to find register for '" + RegName.str() +
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"' (which matches register prefix)";
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throw TGError(II->Instr->TheDef->getLoc(), Err);
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}
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StringRef RegName = II->getSingletonRegisterForToken(i, *this);
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if (RegName != StringRef()) {
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Record *RegRecord = getRegisterRecord(Target, RegName);
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InstructionInfo::Operand Op;
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Op.Class = RegisterClasses[RegRecord];
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Op.OperandInfo = 0;
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assert(Op.Class && Op.Class->Registers.size() == 1 &&
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"Unexpected class for singleton register");
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II->Operands.push_back(Op);
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continue;
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}
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// Check for simple tokens.
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@ -1259,12 +1271,11 @@ static void EmitMatchClassEnumeration(CodeGenTarget &Target,
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}
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/// EmitClassifyOperand - Emit the function to classify an operand.
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static void EmitClassifyOperand(CodeGenTarget &Target,
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AsmMatcherInfo &Info,
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static void EmitClassifyOperand(AsmMatcherInfo &Info,
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raw_ostream &OS) {
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OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n"
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<< " " << Target.getName() << "Operand &Operand = *("
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<< Target.getName() << "Operand*)GOp;\n";
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<< " " << Info.Target.getName() << "Operand &Operand = *("
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<< Info.Target.getName() << "Operand*)GOp;\n";
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// Classify tokens.
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OS << " if (Operand.isToken())\n";
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@ -1279,7 +1290,7 @@ static void EmitClassifyOperand(CodeGenTarget &Target,
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for (std::map<Record*, ClassInfo*>::iterator
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it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
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it != ie; ++it)
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OS << " case " << Target.getName() << "::"
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OS << " case " << Info.Target.getName() << "::"
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<< it->first->getName() << ": return " << it->second->Name << ";\n";
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OS << " }\n";
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OS << " }\n\n";
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@ -1418,8 +1429,7 @@ static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
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/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
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/// definitions.
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static void EmitSubtargetFeatureFlagEnumeration(CodeGenTarget &Target,
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AsmMatcherInfo &Info,
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static void EmitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
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raw_ostream &OS) {
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OS << "// Flags for subtarget features that participate in "
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<< "instruction matching.\n";
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@ -1436,14 +1446,13 @@ static void EmitSubtargetFeatureFlagEnumeration(CodeGenTarget &Target,
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/// EmitComputeAvailableFeatures - Emit the function to compute the list of
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/// available features given a subtarget.
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static void EmitComputeAvailableFeatures(CodeGenTarget &Target,
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AsmMatcherInfo &Info,
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static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
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raw_ostream &OS) {
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std::string ClassName =
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Info.AsmParser->getValueAsString("AsmParserClassName");
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OS << "unsigned " << Target.getName() << ClassName << "::\n"
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<< "ComputeAvailableFeatures(const " << Target.getName()
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OS << "unsigned " << Info.Target.getName() << ClassName << "::\n"
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<< "ComputeAvailableFeatures(const " << Info.Target.getName()
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<< "Subtarget *Subtarget) const {\n";
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OS << " unsigned Features = 0;\n";
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for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
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@ -1561,8 +1570,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
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std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
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// Compute the information on the instructions to match.
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AsmMatcherInfo Info(AsmParser);
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Info.BuildInfo(Target);
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AsmMatcherInfo Info(AsmParser, Target);
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Info.BuildInfo();
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// Sort the instruction table using the partial order on classes. We use
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// stable_sort to ensure that ambiguous instructions are still
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@ -1627,7 +1636,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
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OS << "#undef GET_REGISTER_MATCHER\n\n";
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// Emit the subtarget feature enumeration.
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EmitSubtargetFeatureFlagEnumeration(Target, Info, OS);
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EmitSubtargetFeatureFlagEnumeration(Info, OS);
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// Emit the function to match a register name to number.
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EmitMatchRegisterName(Target, AsmParser, OS);
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@ -1651,13 +1660,13 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
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EmitMatchTokenString(Target, Info.Classes, OS);
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// Emit the routine to classify an operand.
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EmitClassifyOperand(Target, Info, OS);
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EmitClassifyOperand(Info, OS);
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// Emit the subclass predicate routine.
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EmitIsSubclass(Target, Info.Classes, OS);
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// Emit the available features compute function.
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EmitComputeAvailableFeatures(Target, Info, OS);
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EmitComputeAvailableFeatures(Info, OS);
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size_t MaxNumOperands = 0;
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