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Generalize ExpandIntToFP to handle the case where the operand is legal
and it's the result that requires expansion. This code is a little confusing because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type (the integer type) rather than the result type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48206 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5366,20 +5366,25 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
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SDOperand SelectionDAGLegalize::
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SDOperand SelectionDAGLegalize::
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ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
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ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
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MVT::ValueType SourceVT = Source.getValueType();
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MVT::ValueType SourceVT = Source.getValueType();
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assert(getTypeAction(SourceVT) == Expand &&
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bool ExpandSource = getTypeAction(SourceVT) == Expand;
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"This is not an expansion!");
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if (!isSigned) {
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if (!isSigned) {
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// The integer value loaded will be incorrectly if the 'sign bit' of the
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// The integer value loaded will be incorrectly if the 'sign bit' of the
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// incoming integer is set. To handle this, we dynamically test to see if
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// incoming integer is set. To handle this, we dynamically test to see if
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// it is set, and, if so, add a fudge factor.
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// it is set, and, if so, add a fudge factor.
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SDOperand Lo, Hi;
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SDOperand Hi;
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ExpandOp(Source, Lo, Hi);
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if (ExpandSource) {
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SDOperand Lo;
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ExpandOp(Source, Lo, Hi);
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Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
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} else {
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// The comparison for the sign bit will use the entire operand.
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Hi = Source;
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}
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// If this is unsigned, and not supported, first perform the conversion to
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// If this is unsigned, and not supported, first perform the conversion to
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// signed, then adjust the result if the sign bit is set.
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// signed, then adjust the result if the sign bit is set.
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SDOperand SignedConv = ExpandIntToFP(true, DestTy,
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SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
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DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi));
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
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DAG.getConstant(0, Hi.getValueType()),
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DAG.getConstant(0, Hi.getValueType()),
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@ -5437,17 +5442,23 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
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// Expand the source, then glue it back together for the call. We must expand
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// Expand the source, then glue it back together for the call. We must expand
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// the source in case it is shared (this pass of legalize must traverse it).
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// the source in case it is shared (this pass of legalize must traverse it).
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SDOperand SrcLo, SrcHi;
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if (ExpandSource) {
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ExpandOp(Source, SrcLo, SrcHi);
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SDOperand SrcLo, SrcHi;
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Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
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ExpandOp(Source, SrcLo, SrcHi);
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Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
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}
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RTLIB::Libcall LC;
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RTLIB::Libcall LC;
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if (SourceVT == MVT::i64) {
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if (SourceVT == MVT::i64) {
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if (DestTy == MVT::f32)
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if (DestTy == MVT::f32)
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LC = RTLIB::SINTTOFP_I64_F32;
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LC = RTLIB::SINTTOFP_I64_F32;
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else {
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else if (DestTy == MVT::f64)
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assert(DestTy == MVT::f64 && "Unknown fp value type!");
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LC = RTLIB::SINTTOFP_I64_F64;
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LC = RTLIB::SINTTOFP_I64_F64;
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else if (DestTy == MVT::f80)
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LC = RTLIB::SINTTOFP_I64_F80;
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else {
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assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
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LC = RTLIB::SINTTOFP_I64_PPCF128;
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}
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}
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} else if (SourceVT == MVT::i128) {
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} else if (SourceVT == MVT::i128) {
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if (DestTy == MVT::f32)
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if (DestTy == MVT::f32)
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@ -2380,6 +2380,10 @@ SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
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}
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}
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SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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// Don't handle ppc_fp128 here; let it be lowered to a libcall.
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if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
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return SDOperand();
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if (Op.getOperand(0).getValueType() == MVT::i64) {
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if (Op.getOperand(0).getValueType() == MVT::i64) {
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SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
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SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
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SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
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SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
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11
test/CodeGen/PowerPC/int-fp-conv-1.ll
Normal file
11
test/CodeGen/PowerPC/int-fp-conv-1.ll
Normal file
@ -0,0 +1,11 @@
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; RUN: llvm-as < %s | llc -march=ppc64 | grep __floatditf
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define i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
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entry:
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%tmp1213 = uitofp i64 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
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%tmp15 = sub ppc_fp128 %a, %tmp1213 ; <ppc_fp128> [#uses=1]
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%tmp2829 = fptoui ppc_fp128 %tmp15 to i32 ; <i32> [#uses=1]
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%tmp282930 = zext i32 %tmp2829 to i64 ; <i64> [#uses=1]
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%tmp32 = add i64 %tmp282930, 0 ; <i64> [#uses=1]
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ret i64 %tmp32
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}
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