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Fix 80 column violations.

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Original patch by Liu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140385 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-09-23 16:28:10 +00:00
parent 04aa4aee89
commit 0353dab90e
3 changed files with 16 additions and 8 deletions
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3
lib/Target/XCore/XCoreFrameLowering.cpp
View File

@ -100,7 +100,8 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
bool FP = hasFP(MF);
bool Nested = MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::Nest);
bool Nested = MF.getFunction()->
getAttributes().hasAttrSomewhere(Attribute::Nest);
if (Nested) {
loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);

3
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -1415,7 +1415,8 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
// operands are constant canonicalize smallest to RHS.
if ((N0C && !N1C) ||
(N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), N1, N0, N2, N3);
return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
N1, N0, N2, N3);
// lmul(x, 0, a, b)
if (N1C && N1C->isNullValue()) {

18
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -766,19 +766,23 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b),
let Constraints = "$src1 = $dst" in {
def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, immBitp:$src2))]>;
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
immBitp:$src2))]>;
def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
GRRegs:$src2))]>;
def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, immBitp:$src2))]>;
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
immBitp:$src2))]>;
def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
GRRegs:$src2))]>;
def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"andnot $dst, $src2",
@ -825,7 +829,8 @@ def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
let Constraints = "$src = $dst" in
def OUTSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
"outshr res[$r], $src",
[(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
[(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r,
GRRegs:$src))]>;
def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
"inct $dst, res[$r]",
@ -842,7 +847,8 @@ def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r),
let Constraints = "$src = $dst" in
def INSHR_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r, GRRegs:$src),
"inshr $dst, res[$r]",
[(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
[(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r,
GRRegs:$src))]>;
def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val),
"chkct res[$r], $val",