mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
[Hexagon] Deleting old float comparison instruction and updating references to new ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
4ce3b1e4ce
commit
044438aff5
@ -1111,6 +1111,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
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setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
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setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
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setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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@ -1123,6 +1124,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
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setOperationAction(ISD::FADD, MVT::f64, Expand);
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setOperationAction(ISD::FSUB, MVT::f32, Legal);
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setOperationAction(ISD::FSUB, MVT::f64, Expand);
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setOperationAction(ISD::FMUL, MVT::f64, Expand);
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setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
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setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
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@ -1255,7 +1257,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
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setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
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setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
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setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
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setOperationAction(ISD::FMUL, MVT::f64, Expand);
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setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
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@ -154,6 +154,9 @@ def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
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def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
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(F2_sfsub F32:$src1, F32:$src2)>;
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def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
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(F2_sfmpy F32:$src1, F32:$src2)>;
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let Itinerary = M_tc_3x_SLOT23, isCodeGenOnly = 0 in {
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def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
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def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
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@ -495,172 +498,124 @@ def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
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def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
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}
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let isCommutable = 1 in
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def fMUL_rr : ALU64_rr<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2),
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"$dst = sfmpy($src1, $src2)",
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[(set IntRegs:$dst, (fmul IntRegs:$src1, IntRegs:$src2))]>,
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Requires<[HasV5T]>;
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let isCommutable = 1 in
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def fMUL64_rr : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = dfmpy($src1, $src2)",
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[(set DoubleRegs:$dst, (fmul DoubleRegs:$src1,
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DoubleRegs:$src2))]>,
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Requires<[HasV5T]>;
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// Compare.
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let isCompare = 1 in {
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multiclass FCMP64_rr<string OpcStr, PatFrag OpNode> {
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def _rr : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$b, DoubleRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set PredRegs:$dst,
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(OpNode (f64 DoubleRegs:$b), (f64 DoubleRegs:$c)))]>,
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Requires<[HasV5T]>;
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}
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multiclass FCMP32_rr<string OpcStr, PatFrag OpNode> {
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def _rr : ALU64_rr<(outs PredRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
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[(set PredRegs:$dst,
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(OpNode (f32 IntRegs:$b), (f32 IntRegs:$c)))]>,
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Requires<[HasV5T]>;
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}
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}
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defm FCMPOEQ64 : FCMP64_rr<"dfcmp.eq", setoeq>;
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defm FCMPUEQ64 : FCMP64_rr<"dfcmp.eq", setueq>;
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defm FCMPOGT64 : FCMP64_rr<"dfcmp.gt", setogt>;
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defm FCMPUGT64 : FCMP64_rr<"dfcmp.gt", setugt>;
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defm FCMPOGE64 : FCMP64_rr<"dfcmp.ge", setoge>;
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defm FCMPUGE64 : FCMP64_rr<"dfcmp.ge", setuge>;
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defm FCMPOEQ32 : FCMP32_rr<"sfcmp.eq", setoeq>;
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defm FCMPUEQ32 : FCMP32_rr<"sfcmp.eq", setueq>;
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defm FCMPOGT32 : FCMP32_rr<"sfcmp.gt", setogt>;
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defm FCMPUGT32 : FCMP32_rr<"sfcmp.gt", setugt>;
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defm FCMPOGE32 : FCMP32_rr<"sfcmp.ge", setoge>;
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defm FCMPUGE32 : FCMP32_rr<"sfcmp.ge", setuge>;
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// olt.
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def : Pat <(i1 (setolt (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPOGT32_rr IntRegs:$src2, IntRegs:$src1))>,
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(i1 (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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(i1 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (FCMPOGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
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(i1 (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setolt (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
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(i1 (F2_dfcmpgt (f64 (CONST64_Float_Real fpimm:$src2)),
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(f64 DoubleRegs:$src1)))>,
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Requires<[HasV5T]>;
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// gt.
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def : Pat <(i1 (setugt (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT64_rr (f64 DoubleRegs:$src1),
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(i1 (F2_dfcmpgt (f64 DoubleRegs:$src1),
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(f64 (CONST64_Float_Real fpimm:$src2))))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setugt (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT32_rr (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
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(i1 (F2_sfcmpgt (f32 IntRegs:$src1), (f32 (TFRI_f fpimm:$src2))))>,
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Requires<[HasV5T]>;
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// ult.
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def : Pat <(i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1))>,
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(i1 (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT32_rr (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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(i1 (F2_sfcmpgt (f32 (TFRI_f fpimm:$src2)), (f32 IntRegs:$src1)))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
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(i1 (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat <(i1 (setult (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGT64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
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(i1 (F2_dfcmpgt (f64 (CONST64_Float_Real fpimm:$src2)),
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(f64 DoubleRegs:$src1)))>,
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Requires<[HasV5T]>;
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// le.
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// rs <= rt -> rt >= rs.
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def : Pat<(i1 (setole (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPOGE32_rr IntRegs:$src2, IntRegs:$src1))>,
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(i1 (F2_sfcmpge IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setole (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
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(i1 (F2_sfcmpge (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
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Requires<[HasV5T]>;
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// Rss <= Rtt -> Rtt >= Rss.
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def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (FCMPOGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
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(i1 (F2_dfcmpge DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setole (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPOGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
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(i1 (F2_dfcmpge (f64 (CONST64_Float_Real fpimm:$src2)),
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DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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// rs <= rt -> rt >= rs.
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def : Pat<(i1 (setule (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (FCMPUGE32_rr IntRegs:$src2, IntRegs:$src1))>,
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(i1 (F2_sfcmpge IntRegs:$src2, IntRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setule (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGE32_rr (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
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(i1 (F2_sfcmpge (f32 (TFRI_f fpimm:$src2)), IntRegs:$src1))>,
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Requires<[HasV5T]>;
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// Rss <= Rtt -> Rtt >= Rss.
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def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (FCMPUGE64_rr DoubleRegs:$src2, DoubleRegs:$src1))>,
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(i1 (F2_dfcmpge DoubleRegs:$src2, DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setule (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (FCMPUGE64_rr (f64 (CONST64_Float_Real fpimm:$src2)),
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(i1 (F2_dfcmpge (f64 (CONST64_Float_Real fpimm:$src2)),
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DoubleRegs:$src1))>,
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Requires<[HasV5T]>;
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// ne.
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def : Pat<(i1 (setone (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
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(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
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(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setune (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, IntRegs:$src2)))>,
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(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1, DoubleRegs:$src2)))>,
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(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setone (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (C2_not (FCMPOEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
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(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setone (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (C2_not (FCMPOEQ64_rr DoubleRegs:$src1,
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(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1,
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(f64 (CONST64_Float_Real fpimm:$src2)))))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setune (f32 IntRegs:$src1), (fpimm:$src2))),
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(i1 (C2_not (FCMPUEQ32_rr IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
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(i1 (C2_not (F2_sfcmpeq IntRegs:$src1, (f32 (TFRI_f fpimm:$src2)))))>,
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Requires<[HasV5T]>;
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def : Pat<(i1 (setune (f64 DoubleRegs:$src1), (fpimm:$src2))),
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(i1 (C2_not (FCMPUEQ64_rr DoubleRegs:$src1,
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(i1 (C2_not (F2_dfcmpeq DoubleRegs:$src1,
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(f64 (CONST64_Float_Real fpimm:$src2)))))>,
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Requires<[HasV5T]>;
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@ -900,13 +855,13 @@ def TFR_condset_ii_f : ALU32_rr<(outs IntRegs:$dst),
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def : Pat <(select (i1 (setult (f32 IntRegs:$src1), (f32 IntRegs:$src2))),
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(f32 IntRegs:$src3),
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(f32 IntRegs:$src4)),
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(TFR_condset_rr_f (FCMPUGT32_rr IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
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(TFR_condset_rr_f (F2_sfcmpgt IntRegs:$src2, IntRegs:$src1), IntRegs:$src4,
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IntRegs:$src3)>, Requires<[HasV5T]>;
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def : Pat <(select (i1 (setult (f64 DoubleRegs:$src1), (f64 DoubleRegs:$src2))),
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(f64 DoubleRegs:$src3),
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(f64 DoubleRegs:$src4)),
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(TFR_condset_rr64_f (FCMPUGT64_rr DoubleRegs:$src2, DoubleRegs:$src1),
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(TFR_condset_rr64_f (F2_dfcmpgt DoubleRegs:$src2, DoubleRegs:$src1),
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DoubleRegs:$src4, DoubleRegs:$src3)>, Requires<[HasV5T]>;
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// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
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@ -1,7 +1,7 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Check that we generate double precision floating point multiply in V5.
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = dfmpy(r{{[0-9]+}}:{{[0-9]+}}, r{{[0-9]+}}:{{[0-9]+}})
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; CHECK: call __hexagon_muldf3
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define i32 @main() nounwind {
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entry:
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