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https://github.com/c64scene-ar/llvm-6502.git
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Change weight array into a vector and make it as big as the number of
registers (not as the max number of registers). Change toSpill from a std::set into a std::vector<bool>. Use the reverse iterator adapter to do a reverse scan of allocatable registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11061 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -75,10 +75,12 @@ namespace {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// runOnMachineFunction - register allocate the whole function
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bool runOnMachineFunction(MachineFunction&);
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void releaseMemory();
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private:
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/// initIntervalSets - initializa the four interval sets:
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/// unhandled, fixed, active and inactive
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void initIntervalSets(const LiveIntervals::Intervals& li);
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@ -202,6 +204,17 @@ namespace {
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};
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}
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void RA::releaseMemory()
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{
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v2pMap_.clear();
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v2ssMap_.clear();
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unhandled_.clear();
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active_.clear();
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inactive_.clear();
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fixed_.clear();
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}
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bool RA::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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@ -209,8 +222,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
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li_ = &getAnalysis<LiveIntervals>();
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initIntervalSets(li_->getIntervals());
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v2pMap_.clear();
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v2ssMap_.clear();
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memset(regUse_, 0, sizeof(regUse_));
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memset(regUseBackup_, 0, sizeof(regUseBackup_));
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@ -325,8 +336,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
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}
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markPhysRegFree(reg);
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}
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active_.clear();
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inactive_.clear();
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typedef LiveIntervals::Reg2RegMap Reg2RegMap;
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const Reg2RegMap& r2rMap = li_->getJoinedRegMap();
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@ -559,7 +568,7 @@ void RA::processInactiveIntervals(IntervalPtrs::value_type cur)
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namespace {
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template <typename T>
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void updateWeight(T rw[], int reg, T w)
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void updateWeight(std::vector<T>& rw, int reg, T w)
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{
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if (rw[reg] == std::numeric_limits<T>::max() ||
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w == std::numeric_limits<T>::max())
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@ -574,10 +583,7 @@ void RA::assignStackSlotAtInterval(IntervalPtrs::value_type cur)
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DEBUG(std::cerr << "\t\tassigning stack slot at interval "
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<< *cur << ":\n");
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// set all weights to zero
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float regWeight[MRegisterInfo::FirstVirtualRegister];
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for (unsigned i = 0; i < MRegisterInfo::FirstVirtualRegister; ++i)
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regWeight[i] = 0.0F;
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std::vector<float> regWeight(mri_->getNumRegs(), 0.0);
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// for each interval in active
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for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
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@ -639,17 +645,17 @@ void RA::assignStackSlotAtInterval(IntervalPtrs::value_type cur)
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assignVirt2StackSlot(cur->reg);
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}
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else {
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std::set<unsigned> toSpill;
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toSpill.insert(minReg);
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std::vector<bool> toSpill(mri_->getNumRegs(), false);
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toSpill[minReg] = true;
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for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
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toSpill.insert(*as);
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toSpill[*as] = true;
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std::vector<unsigned> spilled;
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for (IntervalPtrs::iterator i = active_.begin();
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i != active_.end(); ) {
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg) &&
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toSpill.find(v2pMap_[reg]) != toSpill.end() &&
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toSpill[v2pMap_[reg]] &&
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cur->overlaps(**i)) {
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spilled.push_back(v2pMap_[reg]);
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DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n');
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@ -664,7 +670,7 @@ void RA::assignStackSlotAtInterval(IntervalPtrs::value_type cur)
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i != inactive_.end(); ) {
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg) &&
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toSpill.find(v2pMap_[reg]) != toSpill.end() &&
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toSpill[v2pMap_[reg]] &&
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cur->overlaps(**i)) {
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DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n');
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assignVirt2StackSlot(reg);
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@ -727,8 +733,10 @@ unsigned RA::getFreeTempPhysReg(unsigned virtReg)
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const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
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// go in reverse allocation order for the temp registers
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for (TargetRegisterClass::iterator i = rc->allocation_order_end(*mf_) - 1;
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i != rc->allocation_order_begin(*mf_) - 1; --i) {
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typedef std::reverse_iterator<TargetRegisterClass::iterator> TRCRevIter;
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for (TRCRevIter
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i(rc->allocation_order_end(*mf_)),
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e(rc->allocation_order_begin(*mf_)); i != e; ++i) {
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unsigned reg = *i;
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if (reserved_[reg] && !regUse_[reg]) {
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DEBUG(std::cerr << mri_->getName(reg) << '\n');
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