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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120533 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,4 +1,4 @@
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//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
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//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -50,9 +50,9 @@ def imm8_255_neg : PatLeaf<(i32 imm), [{
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return Val >= 8 && Val < 256;
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}], imm_neg_XFORM>;
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// Break imm's up into two pieces: an immediate + a left shift.
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// This uses thumb_immshifted to match and thumb_immshifted_val and
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// thumb_immshifted_shamt to get the val/shift pieces.
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// Break imm's up into two pieces: an immediate + a left shift. This uses
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// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
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// to get the val/shift pieces.
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def thumb_immshifted : PatLeaf<(imm), [{
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return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
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}]>;
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@ -208,10 +208,11 @@ def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
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// Change Processor State is a system instruction -- for disassembly only.
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// The singleton $opt operand contains the following information:
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// opt{4-0} = mode ==> don't care
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// opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
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// opt{8-6} = AIF from Inst{2-0}
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// opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
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//
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// opt{4-0} = mode ==> don't care
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// opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
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// opt{8-6} = AIF from Inst{2-0}
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// opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
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//
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// The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
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// CPS which has more options.
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@ -351,9 +352,9 @@ def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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let Inst{7-0} = regs{7-0};
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}
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// All calls clobber the non-callee saved registers. SP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead.
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// All calls clobber the non-callee saved registers. SP is marked as a use to
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// prevent stack-pointer assignments that appear immediately before calls from
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// potentially appearing dead.
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let isCall = 1,
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// On non-Darwin platforms R9 is callee-saved.
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Defs = [R0, R1, R2, R3, R12, LR,
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@ -435,12 +436,11 @@ let isCall = 1,
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Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
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"b\t$target", [(br bb:$target)]>,
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T1Encoding<{1,1,1,0,0,?}>;
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
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"b\t$target", [(br bb:$target)]>,
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T1Encoding<{1,1,1,0,0,?}>;
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// Far jump
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let Defs = [LR] in
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@ -453,7 +453,6 @@ let isBranch = 1, isTerminator = 1 in {
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[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
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list<Predicate> Predicates = [IsThumb, IsThumb1Only];
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}
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}
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}
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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@ -857,10 +856,11 @@ def tBIC : // A8.6.20
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let isCompare = 1, Defs = [CPSR] in {
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//FIXME: Disable CMN, as CCodes are backwards from compare expectations
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// Compare-to-zero still works out, just not the relationals
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//def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
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// "cmn", "\t$lhs, $rhs",
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// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
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// T1DataProcessing<0b1011>;
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//def tCMN : // A8.6.33
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// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
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// IIC_iCMPr,
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// "cmn", "\t$lhs, $rhs",
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// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
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def tCMNz : // A8.6.33
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T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
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@ -1009,7 +1009,7 @@ def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
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T1Special<{1,0,?,?}>;
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} // neverHasSideEffects
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// multiply register
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// Multiply register
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let isCommutable = 1 in
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def tMUL : // A8.6.105 T1
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T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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@ -1214,18 +1214,20 @@ def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
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let Inst = 0xf7fffffe;
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}
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//===----------------------------------------------------------------------===//
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// SJLJ Exception handling intrinsics
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// eh_sjlj_setjmp() is an instruction sequence to store the return
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// address and save #0 in R0 for the non-longjmp case.
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// Since by its nature we may be coming from some other function to get
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// here, and we're using the stack frame for the containing function to
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// save/restore registers, we can't keep anything live in regs across
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// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
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// when we get here from a longjmp(). We force everthing out of registers
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// except for our own input by listing the relevant registers in Defs. By
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// doing so, we also cause the prologue/epilogue code to actively preserve
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// all of the callee-saved resgisters, which is exactly what we want.
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// $val is a scratch register for our use.
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//
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// eh_sjlj_setjmp() is an instruction sequence to store the return address and
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// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
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// from some other function to get here, and we're using the stack frame for the
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// containing function to save/restore registers, we can't keep anything live in
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// regs across the eh_sjlj_setjmp(), else it will almost certainly have been
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// tromped upon when we get here from a longjmp(). We force everthing out of
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// registers except for our own input by listing the relevant registers in
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// Defs. By doing so, we also cause the prologue/epilogue code to actively
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// preserve all of the callee-saved resgisters, which is exactly what we want.
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// $val is a scratch register for our use.
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let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
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hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
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def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
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@ -1324,7 +1326,7 @@ def : T1Pat<(i32 imm0_255_comp:$src),
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// scheduling.
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let isReMaterializable = 1 in
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def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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NoItinerary,
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NoItinerary,
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[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
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imm:$cp))]>,
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Requires<[IsThumb, IsThumb1Only]>;
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