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More refactoring. This time the T1pI pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120532 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
564857f776
commit
1d045ee884
@ -708,6 +708,26 @@ def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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// Arithmetic Instructions.
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//
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// Helper classes for encoding T1pI patterns:
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class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1pI<oops, iops, itin, opc, asm, pattern>,
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T1DataProcessing<opA> {
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bits<3> Rm;
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bits<3> Rn;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rn;
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}
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class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: T1pI<oops, iops, itin, opc, asm, pattern>,
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T1Misc<opA> {
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// Helper classes for encoding T1sI patterns:
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class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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@ -841,17 +861,14 @@ let isCompare = 1, Defs = [CPSR] in {
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// "cmn", "\t$lhs, $rhs",
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// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
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// T1DataProcessing<0b1011>;
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def tCMNz : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
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"cmn", "\t$Rn, $Rm",
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[(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>,
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T1DataProcessing<0b1011> {
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// A8.6.33
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bits<3> Rm;
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bits<3> Rn;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rn;
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}
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}
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def tCMNz : // A8.6.33
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T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iCMPr,
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"cmn", "\t$Rn, $Rm",
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[(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
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} // isCompare = 1, Defs = [CPSR]
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// CMP immediate
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let isCompare = 1, Defs = [CPSR] in {
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@ -877,26 +894,16 @@ def tCMPzi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
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}
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// CMP register
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def tCMPr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
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"cmp", "\t$Rn, $Rm",
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[(ARMcmp tGPR:$Rn, tGPR:$Rm)]>,
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T1DataProcessing<0b1010> {
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// A8.6.36 T1
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bits<3> Rm;
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bits<3> Rn;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rn;
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}
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def tCMPzr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
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"cmp", "\t$Rn, $Rm",
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[(ARMcmpZ tGPR:$Rn, tGPR:$Rm)]>,
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T1DataProcessing<0b1010> {
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// A8.6.36 T1
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bits<3> Rm;
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bits<3> Rn;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rn;
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}
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def tCMPr : // A8.6.36 T1
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T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iCMPr,
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"cmp", "\t$Rn, $Rm",
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[(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
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def tCMPzr : // A8.6.36 T1
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T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
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"cmp", "\t$Rn, $Rm",
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[(ARMcmpZ tGPR:$Rn, tGPR:$Rm)]>;
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def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
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"cmp", "\t$Rn, $Rm", []>,
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@ -1025,48 +1032,33 @@ def tORR : // A8.6.114
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[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
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// Swaps
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def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"rev", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{1,0,1,0,0,0,?}> {
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// A8.6.134
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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def tREV : // A8.6.134
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T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"rev", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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def tREV16 : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"rev16", "\t$Rd, $Rm",
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def tREV16 : // A8.6.135
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T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"rev16", "\t$Rd, $Rm",
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[(set tGPR:$Rd,
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(or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
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(or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
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(or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
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(and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{1,0,1,0,0,1,?}> {
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// A8.6.135
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"revsh", "\t$Rd, $Rm",
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[(set tGPR:$Rd,
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(sext_inreg
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(or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
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(shl tGPR:$Rm, (i32 8))), i16))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{1,0,1,0,1,1,?}> {
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// A8.6.136
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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def tREVSH : // A8.6.136
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T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"revsh", "\t$Rd, $Rm",
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[(set tGPR:$Rd,
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(sext_inreg
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(or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
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(shl tGPR:$Rm, (i32 8))), i16))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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// Rotate right register
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def tROR : // A8.6.139
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@ -1116,70 +1108,43 @@ def tSUBrr : // A8.6.212
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// TODO: A7-96: STMIA - store multiple.
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// Sign-extend byte
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def tSXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"sxtb", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,0,1,?}> {
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// A8.6.222
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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def tSXTB : // A8.6.222
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T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"sxtb", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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// sign-extend short
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def tSXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"sxth", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,0,0,?}> {
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// A8.6.224
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// Sign-extend short
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def tSXTH : // A8.6.224
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T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"sxth", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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// test
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// Test
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let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
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def tTST : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
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"tst", "\t$Rn, $Rm",
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[(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
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T1DataProcessing<0b1000> {
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// A8.6.230
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bits<3> Rm;
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bits<3> Rn;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rn;
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}
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def tTST : // A8.6.230
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T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
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"tst", "\t$Rn, $Rm",
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[(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
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// zero-extend byte
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def tUXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"uxtb", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,1,1,?}> {
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// A8.6.262
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// zero-extend short
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def tUXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
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"uxth", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>,
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T1Misc<{0,0,1,0,1,0,?}> {
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// A8.6.264
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bits<3> Rm;
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bits<3> Rd;
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let Inst{5-3} = Rm;
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let Inst{2-0} = Rd;
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}
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// Zero-extend byte
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def tUXTB : // A8.6.262
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T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"uxtb", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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// Zero-extend short
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def tUXTH : // A8.6.264
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T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"uxth", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
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// Expanded after instruction selection into a branch sequence.
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