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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
Minor cleanups:
- Get the opcode once. - Add a ParserMatchClass to reglist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -285,16 +285,17 @@ def bltarget : Operand<i32> {
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}
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}
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// A list of registers separated by comma. Used by load/store multiple.
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// A list of registers separated by comma. Used by load/store multiple.
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def reglist : Operand<i32> {
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string EncoderMethod = "getRegisterListOpValue";
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let PrintMethod = "printRegisterList";
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}
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def RegListAsmOperand : AsmOperandClass {
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def RegListAsmOperand : AsmOperandClass {
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let Name = "RegList";
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let Name = "RegList";
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let SuperClasses = [];
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let SuperClasses = [];
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}
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}
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def reglist : Operand<i32> {
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string EncoderMethod = "getRegisterListOpValue";
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let ParserMatchClass = RegListAsmOperand;
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let PrintMethod = "printRegisterList";
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}
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// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
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// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
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def cpinst_operand : Operand<i32> {
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def cpinst_operand : Operand<i32> {
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let PrintMethod = "printCPInstOperand";
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let PrintMethod = "printCPInstOperand";
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@ -31,8 +31,10 @@ StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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unsigned Opcode = MI->getOpcode();
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// Check for MOVs and print canonical forms, instead.
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// Check for MOVs and print canonical forms, instead.
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if (MI->getOpcode() == ARM::MOVs) {
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if (Opcode == ARM::MOVs) {
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// FIXME: Thumb variants?
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// FIXME: Thumb variants?
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &MO1 = MI->getOperand(1);
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const MCOperand &MO1 = MI->getOperand(1);
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@ -61,7 +63,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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}
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}
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// A8.6.123 PUSH
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// A8.6.123 PUSH
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if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
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if ((Opcode == ARM::STM_UPD || Opcode == ARM::t2STM_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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MI->getOperand(0).getReg() == ARM::SP) {
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const MCOperand &MO1 = MI->getOperand(2);
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const MCOperand &MO1 = MI->getOperand(2);
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
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@ -74,7 +76,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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}
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}
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// A8.6.122 POP
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// A8.6.122 POP
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if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
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if ((Opcode == ARM::LDM_UPD || Opcode == ARM::t2LDM_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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MI->getOperand(0).getReg() == ARM::SP) {
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const MCOperand &MO1 = MI->getOperand(2);
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const MCOperand &MO1 = MI->getOperand(2);
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
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@ -87,7 +89,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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}
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}
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// A8.6.355 VPUSH
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// A8.6.355 VPUSH
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if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
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if ((Opcode == ARM::VSTMS_UPD || Opcode == ARM::VSTMD_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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MI->getOperand(0).getReg() == ARM::SP) {
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const MCOperand &MO1 = MI->getOperand(2);
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const MCOperand &MO1 = MI->getOperand(2);
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
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@ -100,7 +102,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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}
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}
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// A8.6.354 VPOP
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// A8.6.354 VPOP
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if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
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if ((Opcode == ARM::VLDMS_UPD || Opcode == ARM::VLDMD_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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MI->getOperand(0).getReg() == ARM::SP) {
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const MCOperand &MO1 = MI->getOperand(2);
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const MCOperand &MO1 = MI->getOperand(2);
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
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if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
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@ -113,7 +115,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
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}
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}
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printInstruction(MI, O);
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printInstruction(MI, O);
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}
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}
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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raw_ostream &O) {
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