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stack frame fix and zero FP reg fix

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19857 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-01-27 08:31:19 +00:00
parent 10b400705d
commit 04c868ef50
2 changed files with 19 additions and 12 deletions
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27
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -208,7 +208,7 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (NumBytes <= 32767) {
MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-NumBytes).addReg(Alpha::R30);
MBB.insert(MBBI, MI);
} else if (NumBytes <= 32767 * 65536) {
} else if ((unsigned long)NumBytes <= (unsigned long)32767 * (unsigned long)65536) {
long y = NumBytes / 65536;
if (NumBytes % 65536 > 32767)
++y;
@ -217,7 +217,7 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(-(NumBytes - y * 65536)).addReg(Alpha::R30);
MBB.insert(MBBI, MI);
} else {
std::cerr << "Too big a stack frame\n";
std::cerr << "Too big a stack frame at " << NumBytes << "\n";
abort();
}
}
@ -235,14 +235,21 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
if (NumBytes != 0)
{
if (NumBytes <= 32000) //FIXME: do this better
{
MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes).addReg(Alpha::R30);
MBB.insert(MBBI, MI);
} else {
std::cerr << "Too big a stack frame\n";
abort();
}
if (NumBytes <= 32767) {
MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes).addReg(Alpha::R30);
MBB.insert(MBBI, MI);
} else if ((unsigned long)NumBytes <= (unsigned long)32767 * (unsigned long)65536) {
long y = NumBytes / 65536;
if (NumBytes % 65536 > 32767)
++y;
MI=BuildMI(Alpha::LDAH, 2, Alpha::R30).addImm(y).addReg(Alpha::R30);
MBB.insert(MBBI, MI);
MI=BuildMI(Alpha::LDA, 2, Alpha::R30).addImm(NumBytes - y * 65536).addReg(Alpha::R30);
MBB.insert(MBBI, MI);
} else {
std::cerr << "Too big a stack frame at " << NumBytes << "\n";
abort();
}
}
}

4
lib/Target/Alpha/AlphaRegisterInfo.td
View File

@ -81,13 +81,13 @@ def GPRC : RegisterClass<i64, 64,
//Volitle
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27,
//Non-Volitile
R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, R30, R31]>;
R9, R10, R11, R12, R13, R14, R15, R26, /*R28,*/ R29, R30 /*, R31*/ ]>;
//R28 is reserved for the assembler
//Don't allocate 15, 29, 30, 31
//Allocation volatiles only for now
def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30]>;