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Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if

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the instruction is predicated, reg0 otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-12-06 18:30:57 +00:00
parent d67641b6f8
commit 04f74942f2
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -263,8 +263,8 @@ public:
void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
// FIXME: What belongs here?
Inst.addOperand(MCOperand::CreateReg(0));
unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
Inst.addOperand(MCOperand::CreateReg(RegNum));
}
void addCCOutOperands(MCInst &Inst, unsigned N) const {