Jim Grosbach 04f74942f2 Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
the instruction is predicated, reg0 otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06 18:30:57 +00:00
2010-10-08 00:36:21 +00:00
2010-11-29 18:16:10 +00:00
2010-09-29 17:39:29 +00:00

\Low Level Virtual Machine (LLVM)
================================

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LLVM backend for 6502
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