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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
Regroup some instructions. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -186,31 +186,31 @@ def VLD1q64_UPD : VLD1QWB<0b1100, "64">;
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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// These (dreg triple/quadruple) are for disassembly only.
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// ...with 3 registers (some of these are only for the disassembler):
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class VLD1D3<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr", "", []>;
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class VLD1D4<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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def VLD1d8T : VLD1D3<0b0000, "8">;
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def VLD1d16T : VLD1D3<0b0100, "16">;
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def VLD1d32T : VLD1D3<0b1000, "32">;
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def VLD1d64T : VLD1D3<0b1100, "64">;
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def VLD1d8Q : VLD1D4<0b0000, "8">;
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def VLD1d16Q : VLD1D4<0b0100, "16">;
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def VLD1d32Q : VLD1D4<0b1000, "32">;
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def VLD1d64Q : VLD1D4<0b1100, "64">;
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// ...with address register writeback:
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class VLD1D3WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3\\}, $addr$offset", "$addr.addr = $wb", []>;
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def VLD1d8T : VLD1D3<0b0000, "8">;
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def VLD1d16T : VLD1D3<0b0100, "16">;
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def VLD1d32T : VLD1D3<0b1000, "32">;
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def VLD1d64T : VLD1D3<0b1100, "64">;
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def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
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def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
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def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
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def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
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// ...with 4 registers (some of these are only for the disassembler):
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class VLD1D4<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$addr), IIC_VLD1, "vld1", Dt,
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr", "", []>;
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class VLD1D4WB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0010,op7_4,
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(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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@ -218,10 +218,10 @@ class VLD1D4WB<bits<4> op7_4, string Dt>
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"\\{$dst1, $dst2, $dst3, $dst4\\}, $addr$offset", "$addr.addr = $wb",
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[]>;
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def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
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def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
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def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
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def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
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def VLD1d8Q : VLD1D4<0b0000, "8">;
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def VLD1d16Q : VLD1D4<0b0100, "16">;
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def VLD1d32Q : VLD1D4<0b1000, "32">;
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def VLD1d64Q : VLD1D4<0b1100, "64">;
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def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
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def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
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@ -522,34 +522,34 @@ def VST1q16_UPD : VST1QWB<0b0100, "16">;
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def VST1q32_UPD : VST1QWB<0b1000, "32">;
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def VST1q64_UPD : VST1QWB<0b1100, "64">;
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// These (dreg triple/quadruple) are for disassembly only.
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// ...with 3 registers (some of these are only for the disassembler):
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class VST1D3<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0110, op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr", "", []>;
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class VST1D4<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0010, op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
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[]>;
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def VST1d8T : VST1D3<0b0000, "8">;
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def VST1d16T : VST1D3<0b0100, "16">;
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def VST1d32T : VST1D3<0b1000, "32">;
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def VST1d64T : VST1D3<0b1100, "64">;
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def VST1d8Q : VST1D4<0b0000, "8">;
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def VST1d16Q : VST1D4<0b0100, "16">;
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def VST1d32Q : VST1D4<0b1000, "32">;
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def VST1d64Q : VST1D4<0b1100, "64">;
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// ...with address register writeback:
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class VST1D3WB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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DPR:$src1, DPR:$src2, DPR:$src3),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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def VST1d8T : VST1D3<0b0000, "8">;
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def VST1d16T : VST1D3<0b0100, "16">;
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def VST1d32T : VST1D3<0b1000, "32">;
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def VST1d64T : VST1D3<0b1100, "64">;
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def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
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def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
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def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
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def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
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// ...with 4 registers (some of these are only for the disassembler):
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class VST1D4<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0010, op7_4, (outs),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr", "",
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[]>;
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class VST1D4WB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset,
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@ -557,10 +557,10 @@ class VST1D4WB<bits<4> op7_4, string Dt>
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IIC_VST, "vst1", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
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def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
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def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
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def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
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def VST1d8Q : VST1D4<0b0000, "8">;
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def VST1d16Q : VST1D4<0b0100, "16">;
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def VST1d32Q : VST1D4<0b1000, "32">;
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def VST1d64Q : VST1D4<0b1100, "64">;
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def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
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def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
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