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Rename some VLD1/VST1 instructions to match the implementation, i.e., the

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corresponding NEON instructions, instead of operation they are currently
used for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-03-22 18:13:18 +00:00
parent 58393bc3fd
commit a6979754da
3 changed files with 16 additions and 16 deletions
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8
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1840,7 +1840,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case Intrinsic::arm_neon_vld3: {
unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
ARM::VLD3d32, ARM::VLD3d64 };
ARM::VLD3d32, ARM::VLD1d64T };
unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
ARM::VLD3q16_UPD,
ARM::VLD3q32_UPD };
@ -1852,7 +1852,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case Intrinsic::arm_neon_vld4: {
unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
ARM::VLD4d32, ARM::VLD4d64 };
ARM::VLD4d32, ARM::VLD1d64Q };
unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
ARM::VLD4q16_UPD,
ARM::VLD4q32_UPD };
@ -1892,7 +1892,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case Intrinsic::arm_neon_vst3: {
unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
ARM::VST3d32, ARM::VST3d64 };
ARM::VST3d32, ARM::VST1d64T };
unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
ARM::VST3q16_UPD,
ARM::VST3q32_UPD };
@ -1904,7 +1904,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case Intrinsic::arm_neon_vst4: {
unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
ARM::VST4d32, ARM::VST4d64 };
ARM::VST4d32, ARM::VST1d64Q };
unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
ARM::VST4q16_UPD,
ARM::VST4q32_UPD };

16
lib/Target/ARM/ARMInstrNEON.td
View File

@ -199,12 +199,12 @@ class VLD1D4<bits<4> op7_4, string Dt>
def VLD1d8T : VLD1D3<0b0000, "8">;
def VLD1d16T : VLD1D3<0b0100, "16">;
def VLD1d32T : VLD1D3<0b1000, "32">;
def VLD3d64 : VLD1D3<0b1100, "64">;
def VLD1d64T : VLD1D3<0b1100, "64">;
def VLD1d8Q : VLD1D4<0b0000, "8">;
def VLD1d16Q : VLD1D4<0b0100, "16">;
def VLD1d32Q : VLD1D4<0b1000, "32">;
def VLD4d64 : VLD1D4<0b1100, "64">;
def VLD1d64Q : VLD1D4<0b1100, "64">;
// ...with address register writeback:
class VLD1D3WB<bits<4> op7_4, string Dt>
@ -221,12 +221,12 @@ class VLD1D4WB<bits<4> op7_4, string Dt>
def VLD1d8T_UPD : VLD1D3WB<0b0000, "8">;
def VLD1d16T_UPD : VLD1D3WB<0b0100, "16">;
def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">;
def VLD3d64_UPD : VLD1D3WB<0b1100, "64">;
def VLD3d64T_UPD : VLD1D3WB<0b1100, "64">;
def VLD1d8Q_UPD : VLD1D4WB<0b0000, "8">;
def VLD1d16Q_UPD : VLD1D4WB<0b0100, "16">;
def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">;
def VLD4d64_UPD : VLD1D4WB<0b1100, "64">;
def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">;
// VLD2 : Vector Load (multiple 2-element structures)
class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
@ -536,12 +536,12 @@ class VST1D4<bits<4> op7_4, string Dt>
def VST1d8T : VST1D3<0b0000, "8">;
def VST1d16T : VST1D3<0b0100, "16">;
def VST1d32T : VST1D3<0b1000, "32">;
def VST3d64 : VST1D3<0b1100, "64">;
def VST1d64T : VST1D3<0b1100, "64">;
def VST1d8Q : VST1D4<0b0000, "8">;
def VST1d16Q : VST1D4<0b0100, "16">;
def VST1d32Q : VST1D4<0b1000, "32">;
def VST4d64 : VST1D4<0b1100, "64">;
def VST1d64Q : VST1D4<0b1100, "64">;
// ...with address register writeback:
class VST1D3WB<bits<4> op7_4, string Dt>
@ -560,12 +560,12 @@ class VST1D4WB<bits<4> op7_4, string Dt>
def VST1d8T_UPD : VST1D3WB<0b0000, "8">;
def VST1d16T_UPD : VST1D3WB<0b0100, "16">;
def VST1d32T_UPD : VST1D3WB<0b1000, "32">;
def VST3d64_UPD : VST1D3WB<0b1100, "64">;
def VST1d64T_UPD : VST1D3WB<0b1100, "64">;
def VST1d8Q_UPD : VST1D4WB<0b0000, "8">;
def VST1d16Q_UPD : VST1D4WB<0b0100, "16">;
def VST1d32Q_UPD : VST1D4WB<0b1000, "32">;
def VST4d64_UPD : VST1D4WB<0b1100, "64">;
def VST1d64Q_UPD : VST1D4WB<0b1100, "64">;
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>

8
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@ -83,7 +83,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
case ARM::VLD3d64:
case ARM::VLD1d64T:
case ARM::VLD3LNd8:
case ARM::VLD3LNd16:
case ARM::VLD3LNd32:
@ -128,7 +128,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:
case ARM::VLD4d64:
case ARM::VLD1d64Q:
case ARM::VLD4LNd8:
case ARM::VLD4LNd16:
case ARM::VLD4LNd32:
@ -207,7 +207,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VST3d8:
case ARM::VST3d16:
case ARM::VST3d32:
case ARM::VST3d64:
case ARM::VST1d64T:
case ARM::VST3LNd8:
case ARM::VST3LNd16:
case ARM::VST3LNd32:
@ -252,7 +252,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VST4d8:
case ARM::VST4d16:
case ARM::VST4d32:
case ARM::VST4d64:
case ARM::VST1d64Q:
case ARM::VST4LNd8:
case ARM::VST4LNd16:
case ARM::VST4LNd32: