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Remove invalid instruction encodings.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170291 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2012-12-16 16:46:31 +00:00
parent 1fb0aaa58f
commit 054169be24
1 changed files with 0 additions and 18 deletions
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18
lib/Target/XCore/XCoreInstrFormats.td
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@ -34,90 +34,72 @@ class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FLRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FLU6<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _F2R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FRUS<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _FL2R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _F1R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}
class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-0} = 0;
}