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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Reapply r113875 with additional cleanups.
"The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
ef63c9a9b6
commit
05ae0c6026
@ -218,9 +218,9 @@ class VLD1DWB<bits<4> op7_4, string Dt>
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"vld1", Dt, "\\{$dst\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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class VLD1QWB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
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: NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VLD2,
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"vld1", Dt, "${dst:dregpair}, $addr$offset",
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"vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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def VLD1d8_UPD : VLD1DWB<0b0000, "8">;
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@ -675,8 +675,9 @@ class VST1DWB<bits<4> op7_4, string Dt>
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"vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>;
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class VST1QWB<bits<4> op7_4, string Dt>
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: NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST,
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"vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>;
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(ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
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IIC_VST, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset",
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"$addr.addr = $wb", []>;
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def VST1d8_UPD : VST1DWB<0b0000, "8">;
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def VST1d16_UPD : VST1DWB<0b0100, "16">;
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@ -29,73 +29,27 @@ using namespace llvm;
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#undef MachineInstr
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#undef ARMAsmPrinter
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static unsigned NextReg(unsigned Reg) {
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switch (Reg) {
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// Get the constituent sub-regs for a dregpair from a Q register.
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static std::pair<unsigned, unsigned> GetDRegPair(unsigned QReg) {
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switch (QReg) {
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default:
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assert(0 && "Unexpected register enum");
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case ARM::D0:
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return ARM::D1;
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case ARM::D1:
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return ARM::D2;
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case ARM::D2:
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return ARM::D3;
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case ARM::D3:
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return ARM::D4;
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case ARM::D4:
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return ARM::D5;
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case ARM::D5:
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return ARM::D6;
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case ARM::D6:
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return ARM::D7;
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case ARM::D7:
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return ARM::D8;
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case ARM::D8:
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return ARM::D9;
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case ARM::D9:
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return ARM::D10;
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case ARM::D10:
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return ARM::D11;
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case ARM::D11:
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return ARM::D12;
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case ARM::D12:
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return ARM::D13;
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case ARM::D13:
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return ARM::D14;
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case ARM::D14:
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return ARM::D15;
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case ARM::D15:
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return ARM::D16;
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case ARM::D16:
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return ARM::D17;
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case ARM::D17:
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return ARM::D18;
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case ARM::D18:
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return ARM::D19;
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case ARM::D19:
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return ARM::D20;
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case ARM::D20:
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return ARM::D21;
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case ARM::D21:
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return ARM::D22;
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case ARM::D22:
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return ARM::D23;
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case ARM::D23:
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return ARM::D24;
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case ARM::D24:
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return ARM::D25;
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case ARM::D25:
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return ARM::D26;
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case ARM::D26:
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return ARM::D27;
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case ARM::D27:
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return ARM::D28;
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case ARM::D28:
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return ARM::D29;
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case ARM::D29:
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return ARM::D30;
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case ARM::D30:
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return ARM::D31;
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case ARM::Q0: return std::pair<unsigned, unsigned>(ARM::D0, ARM::D1);
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case ARM::Q1: return std::pair<unsigned, unsigned>(ARM::D2, ARM::D3);
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case ARM::Q2: return std::pair<unsigned, unsigned>(ARM::D4, ARM::D5);
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case ARM::Q3: return std::pair<unsigned, unsigned>(ARM::D6, ARM::D7);
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case ARM::Q4: return std::pair<unsigned, unsigned>(ARM::D8, ARM::D9);
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case ARM::Q5: return std::pair<unsigned, unsigned>(ARM::D10, ARM::D11);
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case ARM::Q6: return std::pair<unsigned, unsigned>(ARM::D12, ARM::D13);
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case ARM::Q7: return std::pair<unsigned, unsigned>(ARM::D14, ARM::D15);
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case ARM::Q8: return std::pair<unsigned, unsigned>(ARM::D16, ARM::D17);
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case ARM::Q9: return std::pair<unsigned, unsigned>(ARM::D18, ARM::D19);
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case ARM::Q10: return std::pair<unsigned, unsigned>(ARM::D20, ARM::D21);
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case ARM::Q11: return std::pair<unsigned, unsigned>(ARM::D22, ARM::D23);
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case ARM::Q12: return std::pair<unsigned, unsigned>(ARM::D24, ARM::D25);
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case ARM::Q13: return std::pair<unsigned, unsigned>(ARM::D26, ARM::D27);
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case ARM::Q14: return std::pair<unsigned, unsigned>(ARM::D28, ARM::D29);
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case ARM::Q15: return std::pair<unsigned, unsigned>(ARM::D30, ARM::D31);
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}
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}
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@ -189,19 +143,11 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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if (Modifier && strcmp(Modifier, "dregpair") == 0) {
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O << '{' << getRegisterName(Reg) << ", "
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<< getRegisterName(NextReg(Reg)) << '}';
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#if 0
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// FIXME: Breaks e.g. ARM/vmul.ll.
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assert(0);
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/*
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unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0);
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unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1);
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O << '{'
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<< getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
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<< '}';*/
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#endif
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std::pair<unsigned, unsigned> dregpair = GetDRegPair(Reg);
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O << '{' << getRegisterName(dregpair.first) << ", "
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<< getRegisterName(dregpair.second) << '}';
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} else if (Modifier && strcmp(Modifier, "lane") == 0) {
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// FIXME
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assert(0);
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/*
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unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
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@ -79,22 +79,9 @@ const char *ARMUtils::OpcodeName(unsigned Opcode) {
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}
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// Return the register enum Based on RegClass and the raw register number.
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// For DRegPair, see comments below.
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// FIXME: Auto-gened?
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static unsigned getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister,
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bool DRegPair = false) {
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if (DRegPair && RegClassID == ARM::QPRRegClassID) {
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// LLVM expects { Dd, Dd+1 } to form a super register; this is not specified
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// in the ARM Architecture Manual as far as I understand it (A8.6.307).
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// Therefore, we morph the RegClassID to be the sub register class and don't
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// subsequently transform the RawRegister encoding when calculating RegNum.
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//
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// See also ARMinstPrinter::printOperand() wrt "dregpair" modifier part
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// where this workaround is meant for.
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RegClassID = ARM::DPRRegClassID;
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}
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static unsigned
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getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
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// For this purpose, we can treat rGPR as if it were GPR.
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if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
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@ -2201,22 +2188,6 @@ static unsigned decodeN3VImm(uint32_t insn) {
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return (insn >> 8) & 0xF;
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}
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static bool UseDRegPair(unsigned Opcode) {
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switch (Opcode) {
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default:
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return false;
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case ARM::VLD1q8_UPD:
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case ARM::VLD1q16_UPD:
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case ARM::VLD1q32_UPD:
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case ARM::VLD1q64_UPD:
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case ARM::VST1q8_UPD:
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case ARM::VST1q16_UPD:
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case ARM::VST1q32_UPD:
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case ARM::VST1q64_UPD:
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return true;
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}
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}
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// VLD*
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// D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
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// VLD*LN*
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@ -2243,10 +2214,9 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
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// We have homogeneous NEON registers for Load/Store.
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unsigned RegClass = 0;
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bool DRegPair = UseDRegPair(Opcode);
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// Double-spaced registers have increments of 2.
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unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1;
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unsigned Inc = DblSpaced ? 2 : 1;
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unsigned Rn = decodeRn(insn);
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unsigned Rm = decodeRm(insn);
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@ -2292,7 +2262,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
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RegClass = OpInfo[OpIdx].RegClass;
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while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
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MI.addOperand(MCOperand::CreateReg(
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getRegisterEnum(B, RegClass, Rd, DRegPair)));
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getRegisterEnum(B, RegClass, Rd)));
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Rd += Inc;
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++OpIdx;
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}
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@ -2311,7 +2281,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
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while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
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MI.addOperand(MCOperand::CreateReg(
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getRegisterEnum(B, RegClass, Rd, DRegPair)));
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getRegisterEnum(B, RegClass, Rd)));
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Rd += Inc;
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++OpIdx;
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}
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@ -9,10 +9,12 @@
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# CHECK: vdup.32 q3, d1[0]
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0x41 0x6c 0xb4 0xf3
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# VLD1q8_UPD (with ${dst:dregpair} operand)
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# CHECK: vld1.8 {d17, d18}, [r6], r5
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0x05 0x1a 0x66 0xf4
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# CHECK: vld1.8 {d17, d18, d19}, [r6], r5
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0x05 0x16 0x66 0xf4
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# CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7
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0x07 0x00 0x22 0xf4
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