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[FastISel][AArch64] Refactor selectAddSub, selectLogicalOp, and SelectShift. NFC.
Small refactor to tidy up the code a little. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217827 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -114,7 +114,7 @@ class AArch64FastISel : public FastISel {
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private:
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// Selection routines.
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bool selectAddSub(const Instruction *I);
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bool selectLogicalOp(const Instruction *I, unsigned ISDOpcode);
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bool selectLogicalOp(const Instruction *I);
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bool SelectLoad(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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@ -1437,29 +1437,52 @@ bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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bool AArch64FastISel::selectAddSub(const Instruction *I) {
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MVT VT;
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if (!isTypeSupported(I->getType(), VT))
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if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
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return false;
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unsigned ResultReg;
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if (I->getOpcode() == Instruction::Add)
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ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
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else if (I->getOpcode() == Instruction::Sub)
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ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
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else
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llvm_unreachable("Unexpected instruction.");
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if (VT.isVector())
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return selectOperator(I, I->getOpcode());
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unsigned ResultReg;
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switch (I->getOpcode()) {
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default:
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llvm_unreachable("Unexpected instruction.");
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case Instruction::Add:
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ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
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break;
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case Instruction::Sub:
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ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
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break;
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}
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if (!ResultReg)
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return false;
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assert(ResultReg && "Couldn't select Add/Sub instruction.");
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updateValueMap(I, ResultReg);
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return true;
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}
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bool AArch64FastISel::selectLogicalOp(const Instruction *I, unsigned ISDOpc) {
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bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
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MVT VT;
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if (!isTypeSupported(I->getType(), VT))
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if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
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return false;
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unsigned ResultReg =
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emitLogicalOp(ISDOpc, VT, I->getOperand(0), I->getOperand(1));
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if (VT.isVector())
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return selectOperator(I, I->getOpcode());
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unsigned ResultReg;
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switch (I->getOpcode()) {
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default:
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llvm_unreachable("Unexpected instruction.");
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case Instruction::And:
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ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
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break;
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case Instruction::Or:
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ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
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break;
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case Instruction::Xor:
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ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
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break;
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}
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if (!ResultReg)
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return false;
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@ -3477,9 +3500,12 @@ bool AArch64FastISel::SelectMul(const Instruction *I) {
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bool AArch64FastISel::SelectShift(const Instruction *I) {
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MVT RetVT;
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if (!isTypeSupported(I->getType(), RetVT))
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if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
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return false;
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if (RetVT.isVector())
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return selectOperator(I, I->getOpcode());
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if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
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unsigned ResultReg = 0;
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uint64_t ShiftVal = C->getZExtValue();
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@ -3604,9 +3630,7 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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break;
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case Instruction::Add:
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case Instruction::Sub:
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if (selectAddSub(I))
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return true;
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break;
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return selectAddSub(I);
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case Instruction::Mul:
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if (!selectBinaryOp(I, ISD::MUL))
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return SelectMul(I);
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@ -3622,21 +3646,11 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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if (SelectShift(I))
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return true;
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break;
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return SelectShift(I);
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case Instruction::And:
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if (selectLogicalOp(I, ISD::AND))
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return true;
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break;
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case Instruction::Or:
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if (selectLogicalOp(I, ISD::OR))
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return true;
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break;
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case Instruction::Xor:
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if (selectLogicalOp(I, ISD::XOR))
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return true;
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break;
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return selectLogicalOp(I);
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case Instruction::Br:
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return SelectBranch(I);
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case Instruction::IndirectBr:
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