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[FastISel][AArch64] Refactor code to use isTypeSupported. NFC.
Gets rid of isLoadStoreTypeLegal and replace it with isTypeSupported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217826 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -135,8 +135,7 @@ private:
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
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bool isTypeSupported(Type *Ty, MVT &VT);
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bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
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bool isValueAvailable(const Value *V) const;
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bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool ComputeCallAddress(const Value *V, Address &Addr);
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@ -676,25 +675,12 @@ bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
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return TLI.isTypeLegal(VT);
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}
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bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
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if (isTypeLegal(Ty, VT))
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return true;
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// If this is a type than can be sign or zero-extended to a basic operation
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// go ahead and accept it now. For stores, this reflects truncation.
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if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
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return true;
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return false;
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}
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/// \brief Determine if the value type is supported by FastISel.
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///
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/// FastISel for AArch64 can handle more value types than are legal. This adds
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/// simple value type such as i1, i8, and i16.
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/// Vectors on the other side are not supported yet.
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bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT) {
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if (Ty->isVectorTy())
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bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
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if (Ty->isVectorTy() && !IsVectorAllowed)
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return false;
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if (isTypeLegal(Ty, VT))
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@ -1486,7 +1472,8 @@ bool AArch64FastISel::SelectLoad(const Instruction *I) {
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// Verify we have a legal type before going any further. Currently, we handle
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// simple types that will directly fit in a register (i32/f32/i64/f64) or
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// those that can be sign or zero-extended to a basic operation (i1/i8/i16).
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if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
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if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) ||
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cast<LoadInst>(I)->isAtomic())
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return false;
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// See if we can handle this address.
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@ -1583,7 +1570,7 @@ bool AArch64FastISel::SelectStore(const Instruction *I) {
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// Verify we have a legal type before going any further. Currently, we handle
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// simple types that will directly fit in a register (i32/f32/i64/f64) or
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// those that can be sign or zero-extended to a basic operation (i1/i8/i16).
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if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
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if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) ||
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cast<StoreInst>(I)->isAtomic())
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return false;
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