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Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but
not associative. Add [SU]REM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23508 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -65,14 +65,14 @@ class SDTypeProfile<int numresults, int numoperands,
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}
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// Builtin profiles.
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def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
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def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
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def SDTBinOp : SDTypeProfile<1, 2, [ // add, mul, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
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]>;
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def SDTIntBinOp : SDTypeProfile<1, 2, [ // and, or, xor, udiv, etc.
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def SDTImm : SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
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def SDTVT : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
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def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
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]>;
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def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
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]>;
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def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
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SDTCisSameAs<0, 1>, SDTCisInt<0>
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]>;
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@ -106,21 +106,29 @@ def node;
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def imm : SDNode<"ISD::Constant" , SDTImm , [], "ConstantSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTVT , [], "VTSDNode">;
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def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
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[SDNPCommutative, SDNPAssociative]>;
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def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
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def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
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def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
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def and : SDNode<"ISD::AND" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def add : SDNode<"ISD::ADD" , SDTBinOp ,
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[SDNPCommutative, SDNPAssociative]>;
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def sub : SDNode<"ISD::SUB" , SDTBinOp>;
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def mul : SDNode<"ISD::MUL" , SDTBinOp ,
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[SDNPCommutative, SDNPAssociative]>;
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def sdiv : SDNode<"ISD::SDIV" , SDTBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
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def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
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def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
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def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
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def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
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def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
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def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
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def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
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