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Add add reg-reg and reg-imm patterns

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 13:30:15 +00:00
parent 1cc9dc7267
commit 0676d2887a
4 changed files with 45 additions and 1 deletions
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24
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -47,3 +47,27 @@ def MOV64ri : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"lghi\t{$dst, $src}",
[(set GR64:$dst, imm:$src)]>;
}
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
let isTwoAddress = 1 in {
let Defs = [PSW] in {
let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
// FIXME: Provide proper encoding!
def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"agr\t{$dst, $src2}",
[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
(implicit PSW)]>;
}
// FIXME: Provide proper encoding!
def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"aghi\t{$dst, $src2}",
[(set GR64:$dst, (add GR64:$src1, imm:$src2)),
(implicit PSW)]>;
} // Defs = [PSW]
} // isTwoAddress = 1

10
lib/Target/SystemZ/SystemZRegisterInfo.td
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@ -62,8 +62,11 @@ def F13 : FPR<13, "f13">, DwarfRegNum<[29]>;
def F14 : FPR<14, "f14">, DwarfRegNum<[30]>;
def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
// Status register
def PSW : SystemZReg<"psw">;
/// Register classes
def GR64 : RegisterClass<"SystemZ", [i64], 16,
def GR64 : RegisterClass<"SystemZ", [i64], 64,
// Volatile registers
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R12, R13,
// Frame pointer, sometimes allocable
@ -91,3 +94,8 @@ def GR64 : RegisterClass<"SystemZ", [i64], 16,
def FP64 : RegisterClass<"SystemZ", [f64], 64,
[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>;
// Status flags registers.
def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
let CopyCost = -1; // Don't allow copying of status registers.
}

6
test/CodeGen/SystemZ/02-RetAdd.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = add i64 %a, %b
ret i64 %c
}

6
test/CodeGen/SystemZ/02-RetAddImm.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = add i64 %a, 1
ret i64 %c
}