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https://github.com/c64scene-ar/llvm-6502.git
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0676d2887a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
3.4 KiB
TableGen
102 lines
3.4 KiB
TableGen
//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class SystemZReg<string n> : Register<n> {
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let Namespace = "SystemZ";
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}
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// We identify all our registers with a 4-bit ID, for consistency's sake.
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// GPR - One of the 16 64-bit general-purpose registers
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class GPR<bits<4> num, string n> : SystemZReg<n> {
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field bits<4> Num = num;
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}
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// FPR - One of the 16 64-bit floating-point registers
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class FPR<bits<4> num, string n> : SystemZReg<n> {
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field bits<4> Num = num;
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}
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// General-purpose registers
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def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>;
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def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : GPR<10, "r10">, DwarfRegNum<[10]>;
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def R11 : GPR<11, "r11">, DwarfRegNum<[11]>;
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def R12 : GPR<12, "r12">, DwarfRegNum<[12]>;
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def R13 : GPR<13, "r13">, DwarfRegNum<[13]>;
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def R14 : GPR<14, "r14">, DwarfRegNum<[14]>;
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def R15 : GPR<15, "r15">, DwarfRegNum<[15]>;
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// Floating-point registers
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def F0 : FPR< 0, "f0">, DwarfRegNum<[16]>;
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def F1 : FPR< 1, "f1">, DwarfRegNum<[17]>;
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def F2 : FPR< 2, "f2">, DwarfRegNum<[18]>;
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def F3 : FPR< 3, "f3">, DwarfRegNum<[19]>;
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def F4 : FPR< 4, "f4">, DwarfRegNum<[20]>;
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def F5 : FPR< 5, "f5">, DwarfRegNum<[21]>;
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def F6 : FPR< 6, "f6">, DwarfRegNum<[22]>;
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def F7 : FPR< 7, "f7">, DwarfRegNum<[23]>;
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def F8 : FPR< 8, "f8">, DwarfRegNum<[24]>;
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def F9 : FPR< 9, "f9">, DwarfRegNum<[25]>;
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def F10 : FPR<10, "f10">, DwarfRegNum<[26]>;
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def F11 : FPR<11, "f11">, DwarfRegNum<[27]>;
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def F12 : FPR<12, "f12">, DwarfRegNum<[28]>;
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def F13 : FPR<13, "f13">, DwarfRegNum<[29]>;
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def F14 : FPR<14, "f14">, DwarfRegNum<[30]>;
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def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
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// Status register
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def PSW : SystemZReg<"psw">;
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/// Register classes
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def GR64 : RegisterClass<"SystemZ", [i64], 64,
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// Volatile registers
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[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R12, R13,
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// Frame pointer, sometimes allocable
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R11,
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// Volatile, but not allocable
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R14, R15]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GR64Class::iterator
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GR64Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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// Depending on whether the function uses frame pointer or not, last 2 or 3
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// registers on the list above are reserved
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if (RI->hasFP(MF))
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return end()-3;
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else
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return end()-2;
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}
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}];
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}
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def FP64 : RegisterClass<"SystemZ", [f64], 64,
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[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>;
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// Status flags registers.
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def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
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let CopyCost = -1; // Don't allow copying of status registers.
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}
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