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Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU.
- This is an initial step towards -march=native support in Clang, and towards eliminating host dependencies in the targets. See PR5389. - Patch by Roman Divacky! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar
parent
e79fddedca
commit
067d024b05
@ -41,6 +41,12 @@ namespace sys {
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/// CPU_TYPE-VENDOR-KERNEL-OPERATING_SYSTEM
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std::string getHostTriple();
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/// getHostCPUName - Get the LLVM name for the host CPU. The particular format
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/// of the name is target dependent, and suitable for passing as -mcpu to the
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/// target which matches the host.
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///
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/// \return - The host CPU name, or empty if the CPU could not be determined.
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std::string getHostCPUName();
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}
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}
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@ -13,6 +13,7 @@
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#include "llvm/System/Host.h"
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#include "llvm/Config/config.h"
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#include <string.h>
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// Include the platform-specific parts of this class.
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#ifdef LLVM_ON_UNIX
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@ -22,3 +23,198 @@
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#include "Win32/Host.inc"
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#endif
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//===----------------------------------------------------------------------===//
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//
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// Implementations of the CPU detection routines
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//
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//===----------------------------------------------------------------------===//
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using namespace llvm;
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuid(registers, value);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#endif
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#endif
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return true;
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}
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static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (Family == 6 || Family == 0xf) {
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if (Family == 0xf)
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// Examine extended family ID if family ID is F.
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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}
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#endif
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std::string sys::getHostCPUName() {
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#if defined(__x86_64__) || defined(__i386__)
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = 0;
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unsigned Model = 0;
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DetectX86FamilyModel(EAX, Family, Model);
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GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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bool HasSSE3 = (ECX & 0x1);
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union {
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unsigned u[3];
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char c[12];
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} text;
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GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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switch (Family) {
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case 3:
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return "i386";
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 4: return "pentium-mmx";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 1: return "pentiumpro";
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case 3:
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case 5:
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case 6: return "pentium2";
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case 7:
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case 8:
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case 10:
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case 11: return "pentium3";
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case 9:
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case 13: return "pentium-m";
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case 14: return "yonah";
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case 15:
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case 22: // Celeron M 540
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return "core2";
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case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
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return "penryn";
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default: return "i686";
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}
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case 15: {
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switch (Model) {
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case 3:
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case 4:
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case 6: // same as 4, but 65nm
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return (Em64T) ? "nocona" : "prescott";
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case 26:
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return "corei7";
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case 28:
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return "atom";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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}
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default:
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return "generic";
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}
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} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
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// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 4: return "athlon-tbird";
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case 6:
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case 7:
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case 8: return "athlon-mp";
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case 10: return "athlon-xp";
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default: return "athlon";
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}
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case 15:
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if (HasSSE3) {
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return "k8-sse3";
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} else {
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switch (Model) {
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case 1: return "opteron";
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case 5: return "athlon-fx"; // also opteron
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default: return "athlon64";
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}
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}
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case 16:
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return "amdfam10";
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default:
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return "generic";
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}
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} else {
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return "generic";
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}
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#else
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return "generic";
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#endif
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}
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@ -18,6 +18,7 @@
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#include "llvm/GlobalValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/System/Host.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallVector.h"
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@ -258,118 +259,6 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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}
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}
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static const char *GetCurrentX86CPU() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = 0;
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unsigned Model = 0;
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DetectFamilyModel(EAX, Family, Model);
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GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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bool HasSSE3 = (ECX & 0x1);
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union {
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unsigned u[3];
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char c[12];
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} text;
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GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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switch (Family) {
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case 3:
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return "i386";
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 4: return "pentium-mmx";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 1: return "pentiumpro";
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case 3:
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case 5:
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case 6: return "pentium2";
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case 7:
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case 8:
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case 10:
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case 11: return "pentium3";
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case 9:
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case 13: return "pentium-m";
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case 14: return "yonah";
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case 15:
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case 22: // Celeron M 540
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return "core2";
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case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
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return "penryn";
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default: return "i686";
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}
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case 15: {
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switch (Model) {
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case 3:
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case 4:
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case 6: // same as 4, but 65nm
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return (Em64T) ? "nocona" : "prescott";
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case 26:
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return "corei7";
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case 28:
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return "atom";
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default:
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return (Em64T) ? "x86-64" : "pentium4";
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}
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}
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default:
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return "generic";
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}
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} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
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// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
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// appears to be no way to generate the wide variety of AMD-specific targets
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// from the information returned from CPUID.
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switch (Family) {
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case 4:
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return "i486";
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case 5:
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switch (Model) {
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case 6:
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case 7: return "k6";
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case 8: return "k6-2";
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case 9:
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case 13: return "k6-3";
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default: return "pentium";
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}
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case 6:
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switch (Model) {
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case 4: return "athlon-tbird";
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case 6:
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case 7:
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case 8: return "athlon-mp";
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case 10: return "athlon-xp";
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default: return "athlon";
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}
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case 15:
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if (HasSSE3) {
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return "k8-sse3";
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} else {
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switch (Model) {
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case 1: return "opteron";
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case 5: return "athlon-fx"; // also opteron
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default: return "athlon64";
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}
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}
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case 16:
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return "amdfam10";
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default:
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return "generic";
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}
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} else {
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return "generic";
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}
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}
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X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
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bool is64Bit)
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: PICStyle(PICStyles::None)
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@ -396,7 +285,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
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// Determine default and user specified characteristics
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if (!FS.empty()) {
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// If feature string is not empty, parse features string.
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std::string CPU = GetCurrentX86CPU();
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std::string CPU = sys::getHostCPUName();
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ParseSubtargetFeatures(FS, CPU);
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// All X86-64 CPUs also have SSE2, however user might request no SSE via
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// -mattr, so don't force SSELevel here.
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