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Move the constant-folding support for FP_ROUND in SelectionDAG from the one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point.

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Zap a testcase that this allows us to completely fold away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154447 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2012-04-10 22:46:53 +00:00
parent 83f17f25fc
commit 06886aaaeb
2 changed files with 12 additions and 19 deletions
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11
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2428,7 +2428,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
case ISD::FABS:
V.clearSign();
return getConstantFP(V, VT);
case ISD::FP_ROUND:
case ISD::FP_EXTEND: {
bool ignored;
// This can return overflow, underflow, or inexact; we don't care.
@ -2994,6 +2993,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
default: break;
}
}
if (Opcode == ISD::FP_ROUND) {
APFloat V = N1CFP->getValueAPF(); // make copy
bool ignored;
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
(void)V.convert(*EVTToAPFloatSemantics(VT),
APFloat::rmNearestTiesToEven, &ignored);
return getConstantFP(V, VT);
}
}
// Canonicalize an UNDEF to the RHS, even over a constant.

20
test/CodeGen/ARM/fcopysign.ll
View File

@ -40,26 +40,10 @@ entry:
ret double %1
}
; rdar://9059537
define i32 @test4() ssp {
; rdar://9287902
define float @test4() nounwind {
entry:
; SOFT: test4:
; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
; This S-reg must be the first sub-reg of the last D-reg on vbsl.
; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]]
; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
%call80 = tail call double @copysign(double 1.000000e+00, double undef)
%conv81 = fptrunc double %call80 to float
%tmp88 = bitcast float %conv81 to i32
ret i32 %tmp88
}
; rdar://9287902
define float @test5() nounwind {
entry:
; SOFT: test5:
; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
; SOFT: vshr.u64 [[REG7]], [[REG7]], #32