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Move the constant-folding support for FP_ROUND in SelectionDAG from the one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point.
Zap a testcase that this allows us to completely fold away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154447 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2428,7 +2428,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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case ISD::FABS:
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V.clearSign();
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return getConstantFP(V, VT);
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case ISD::FP_ROUND:
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case ISD::FP_EXTEND: {
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bool ignored;
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// This can return overflow, underflow, or inexact; we don't care.
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@ -2994,6 +2993,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
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default: break;
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}
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}
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if (Opcode == ISD::FP_ROUND) {
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APFloat V = N1CFP->getValueAPF(); // make copy
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bool ignored;
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// This can return overflow, underflow, or inexact; we don't care.
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// FIXME need to be more flexible about rounding mode.
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(void)V.convert(*EVTToAPFloatSemantics(VT),
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APFloat::rmNearestTiesToEven, &ignored);
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return getConstantFP(V, VT);
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}
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}
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// Canonicalize an UNDEF to the RHS, even over a constant.
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@ -40,26 +40,10 @@ entry:
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ret double %1
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}
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; rdar://9059537
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define i32 @test4() ssp {
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; rdar://9287902
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define float @test4() nounwind {
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entry:
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; SOFT: test4:
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; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
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; This S-reg must be the first sub-reg of the last D-reg on vbsl.
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; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]]
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; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
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; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
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; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
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%call80 = tail call double @copysign(double 1.000000e+00, double undef)
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%conv81 = fptrunc double %call80 to float
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%tmp88 = bitcast float %conv81 to i32
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ret i32 %tmp88
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}
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; rdar://9287902
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define float @test5() nounwind {
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entry:
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; SOFT: test5:
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; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
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; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
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; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
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