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Add operand encoding bits for SMC and SVC in ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1295,14 +1295,18 @@ def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
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// Secure Monitor Call is a system instruction -- for disassembly only
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def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{23-20} = 0b0110;
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let Inst{7-4} = 0b0111;
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bits<4> opt;
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let Inst{23-4} = 0b01100000000000000111;
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let Inst{3-0} = opt;
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}
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// Supervisor Call (Software Interrupt) -- for disassembly only
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let isCall = 1 in {
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def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
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[/* For disassembly only; pattern left blank */]>;
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[/* For disassembly only; pattern left blank */]> {
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bits<24> svc;
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let Inst{23-0} = svc;
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}
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}
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// Store Return State is a system instruction -- for disassembly only
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