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[FastISel][X86] Use XOR to materialize the "0" value.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215594 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
2014-08-13 22:22:17 +00:00
parent f245d9aa77
commit 0701e5d43b
5 changed files with 34 additions and 11 deletions
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23
lib/Target/X86/X86FastISel.cpp
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@@ -3107,6 +3107,29 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
return 0;
uint64_t Imm = CI->getZExtValue();
if (Imm == 0) {
unsigned SrcReg = FastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type");
case MVT::i1:
case MVT::i8:
return FastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Kill=*/true,
X86::sub_8bit);
case MVT::i16:
return FastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
X86::sub_16bit);
case MVT::i32:
return SrcReg;
case MVT::i64: {
unsigned ResultReg = createResultReg(&X86::GR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
.addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
return ResultReg;
}
}
}
unsigned Opc = 0;
switch (VT.SimpleTy) {
default: llvm_unreachable("Unexpected value type");