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RALinScan::attemptTrivialCoalescing() was returning a virtual register instead of the physical register it is allocated to. This resulted in virtual register(s) being added the live-in sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72890 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -398,7 +398,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
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}
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++NumCoalesce;
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return SrcReg;
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return PhysReg;
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}
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return Reg;
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@ -555,8 +555,11 @@ void RALinScan::linearScan()
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re = mri_->reg_end(); ri != re; ++ri) {
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MachineInstr *UseMI = &*ri;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (Seen.insert(UseMBB))
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if (Seen.insert(UseMBB)) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"Adding a virtual register to livein set?");
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UseMBB->addLiveIn(Reg);
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}
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}
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}
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}
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@ -565,8 +568,11 @@ void RALinScan::linearScan()
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const LiveRange &LR = *I;
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if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
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for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
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if (LiveInMBBs[i] != EntryMBB)
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if (LiveInMBBs[i] != EntryMBB) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"Adding a virtual register to livein set?");
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LiveInMBBs[i]->addLiveIn(Reg);
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}
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LiveInMBBs.clear();
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}
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}
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48
test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
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48
test/CodeGen/X86/2009-06-04-VirtualLiveIn.ll
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@ -0,0 +1,48 @@
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; RUN: llvm-as < %s | llc -march=x86
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type { %struct.GAP } ; type %0
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type { i16, i8, i8 } ; type %1
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type { [2 x i32], [2 x i32] } ; type %2
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type { %struct.rec* } ; type %3
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%struct.FILE_POS = type { i8, i8, i16, i32 }
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%struct.FIRST_UNION = type { %struct.FILE_POS }
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%struct.FOURTH_UNION = type { %struct.STYLE }
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%struct.GAP = type { i8, i8, i16 }
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%struct.LIST = type { %struct.rec*, %struct.rec* }
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%struct.SECOND_UNION = type { %1 }
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%struct.STYLE = type { %0, %0, i16, i16, i32 }
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%struct.THIRD_UNION = type { %2 }
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%struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, %3, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
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%struct.rec = type { %struct.head_type }
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define fastcc void @MinSize(%struct.rec* %x) nounwind {
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entry:
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%tmp13 = load i8* undef, align 4 ; <i8> [#uses=3]
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%tmp14 = zext i8 %tmp13 to i32 ; <i32> [#uses=2]
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switch i32 %tmp14, label %bb1109 [
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i32 42, label %bb246
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]
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bb246: ; preds = %entry, %entry
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switch i8 %tmp13, label %bb249 [
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i8 42, label %bb269
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i8 44, label %bb269
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]
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bb249: ; preds = %bb246
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%tmp3240 = icmp eq i8 %tmp13, 0 ; <i1> [#uses=1]
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br i1 %tmp3240, label %bb974, label %bb269
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bb269:
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%tmp3424 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 0, i32 0, i32 1 ; <%struct.rec**> [#uses=0]
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unreachable
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bb974:
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unreachable
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bb1109: ; preds = %entry
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call fastcc void @Image(i32 %tmp14) nounwind ; <i8*> [#uses=0]
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unreachable
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}
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declare fastcc void @Image(i32) nounwind
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