6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Finegrainify namespacification

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-23 18:38:20 +00:00
parent e699b16a76
commit 0742b59913
4 changed files with 12 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/MachineCodeEmitter.cpp
View File

@ -15,8 +15,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Function.h"
#include <fstream>
namespace llvm {
using namespace llvm;
namespace {
struct DebugMachineCodeEmitter : public MachineCodeEmitter {
@ -173,5 +172,3 @@ MachineCodeEmitter *
MachineCodeEmitter::createFilePrinterEmitter(MachineCodeEmitter &MCE) {
return new FilePrinterEmitter(MCE, std::cerr);
}
} // End llvm namespace

16
lib/CodeGen/MachineInstr.cpp
View File

@ -21,8 +21,7 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
#include "Support/LeakDetector.h"
namespace llvm {
using namespace llvm;
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
@ -31,7 +30,9 @@ namespace llvm {
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
extern const TargetInstrDescriptor *TargetInstrDescriptors;
namespace {
extern const TargetInstrDescriptor *TargetInstrDescriptors;
}
// Constructor for instructions with variable #operands
MachineInstr::MachineInstr(short opcode, unsigned numOperands)
@ -291,7 +292,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
// Specialize printing if op#0 is definition
if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
llvm::print(getOperand(0), OS, TM);
::print(getOperand(0), OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
}
@ -302,7 +303,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
if (i != StartOp)
OS << ",";
OS << " ";
llvm::print(mop, OS, TM);
::print(mop, OS, TM);
if (mop.isDef())
if (mop.isUse())
@ -441,12 +442,9 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
break;
}
if (MO.flags &
(MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
OS << ")";
return OS;
}
} // End llvm namespace

5
lib/CodeGen/MachineInstrAnnot.cpp
View File

@ -17,8 +17,7 @@
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/iOther.h"
#include "llvm/Type.h"
namespace llvm {
using namespace llvm;
CallArgsDescriptor::CallArgsDescriptor(CallInst* _callInstr,
TmpInstruction* _retAddrReg,
@ -77,5 +76,3 @@ CallArgsDescriptor *CallArgsDescriptor::get(const MachineInstr* MI)
assert(desc->getCallInst()==callInstr && "Incorrect call args descriptor?");
return desc;
}
} // End llvm namespace

8
lib/CodeGen/PHIElimination.cpp
View File

@ -13,6 +13,7 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
@ -21,8 +22,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CFG.h"
#include "Support/STLExtras.h"
namespace llvm {
using namespace llvm;
namespace {
struct PNE : public MachineFunctionPass {
@ -56,7 +56,7 @@ namespace {
}
const PassInfo *PHIEliminationID = X.getPassInfo();
const PassInfo *llvm::PHIEliminationID = X.getPassInfo();
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
/// predecessor basic blocks.
@ -250,5 +250,3 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
}
return true;
}
} // End llvm namespace