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Fix live-out reg logic to not insert over-aggressive AssertZExt
instructions. This fixes lua. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68083 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4587,15 +4587,15 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
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isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
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else if (NumSignBits > RegSize-8)
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isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
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else if (NumZeroBits >= RegSize-9)
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else if (NumZeroBits >= RegSize-8)
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isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
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else if (NumSignBits > RegSize-16)
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isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
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else if (NumZeroBits >= RegSize-17)
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else if (NumZeroBits >= RegSize-16)
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isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
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else if (NumSignBits > RegSize-32)
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isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
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else if (NumZeroBits >= RegSize-33)
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else if (NumZeroBits >= RegSize-32)
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isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
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if (FromVT != MVT::Other) {
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20
test/CodeGen/X86/live-out-reg-info.ll
Normal file
20
test/CodeGen/X86/live-out-reg-info.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llvm-as < %s | llc -march=x86-64 | grep testl
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; Make sure dagcombine doesn't eliminate the comparison due
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; to an off-by-one bug with ComputeMaskedBits information.
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declare void @qux()
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define void @foo(i32 %a) {
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%t0 = lshr i32 %a, 23
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br label %next
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next:
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%t1 = and i32 %t0, 256
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%t2 = icmp eq i32 %t1, 0
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br i1 %t2, label %true, label %false
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true:
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call void @qux()
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ret void
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false:
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ret void
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}
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