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Fix live-out reg logic to not insert over-aggressive AssertZExt

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instructions. This fixes lua.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68083 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-03-31 01:38:29 +00:00
parent 4d95232469
commit 07c26ee87e
2 changed files with 23 additions and 3 deletions
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6
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -4587,15 +4587,15 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
else if (NumSignBits > RegSize-8)
isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
else if (NumZeroBits >= RegSize-9)
else if (NumZeroBits >= RegSize-8)
isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16)
isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-17)
else if (NumZeroBits >= RegSize-16)
isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32)
isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-33)
else if (NumZeroBits >= RegSize-32)
isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
if (FromVT != MVT::Other) {

20
test/CodeGen/X86/live-out-reg-info.ll Normal file
View File

@ -0,0 +1,20 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep testl
; Make sure dagcombine doesn't eliminate the comparison due
; to an off-by-one bug with ComputeMaskedBits information.
declare void @qux()
define void @foo(i32 %a) {
%t0 = lshr i32 %a, 23
br label %next
next:
%t1 = and i32 %t0, 256
%t2 = icmp eq i32 %t1, 0
br i1 %t2, label %true, label %false
true:
call void @qux()
ret void
false:
ret void
}