mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-24 08:29:39 +00:00
Eliminate a bunch of redundant tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77558 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
cf661e2c56
commit
084d1ba5ad
@ -270,42 +270,27 @@ def : SubRegSet<1, [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
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// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
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// cannot be encoded.
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def GR8 : RegisterClass<"X86", [i8], 8,
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[AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
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[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
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R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate SPL or BPL.
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static const unsigned X86_GR8_AO_64_fp[] = {
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X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
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X86::R8B, X86::R9B, X86::R10B, X86::R11B,
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X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B
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};
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// If not, just don't allocate SPL.
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static const unsigned X86_GR8_AO_64[] = {
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X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
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X86::R8B, X86::R9B, X86::R10B, X86::R11B,
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X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
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};
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// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
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static const unsigned X86_GR8_AO_32[] = {
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X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH
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};
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GR8Class::iterator
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GR8Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (!Subtarget.is64Bit())
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return X86_GR8_AO_32;
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else if (RI->hasFP(MF))
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return X86_GR8_AO_64_fp;
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else
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if (Subtarget.is64Bit())
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return X86_GR8_AO_64;
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else
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return begin();
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}
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GR8Class::iterator
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@ -313,11 +298,15 @@ def GR8 : RegisterClass<"X86", [i8], 8,
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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// Does the function dedicate RBP / EBP to being a frame ptr?
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if (!Subtarget.is64Bit())
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return array_endof(X86_GR8_AO_32);
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// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
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return begin() + 8;
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else if (RI->hasFP(MF))
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return array_endof(X86_GR8_AO_64_fp);
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// If so, don't allocate SPL or BPL.
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return array_endof(X86_GR8_AO_64) - 1;
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else
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// If not, just don't allocate SPL.
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return array_endof(X86_GR8_AO_64);
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}
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}];
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@ -333,42 +322,20 @@ def GR16 : RegisterClass<"X86", [i16], 16,
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate SP or BP.
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static const unsigned X86_GR16_AO_64_fp[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
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X86::R8W, X86::R9W, X86::R10W, X86::R11W,
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X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W
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};
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static const unsigned X86_GR16_AO_32_fp[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
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};
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// If not, just don't allocate SP.
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static const unsigned X86_GR16_AO_64[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
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X86::R8W, X86::R9W, X86::R10W, X86::R11W,
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X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
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};
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static const unsigned X86_GR16_AO_32[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
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};
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GR16Class::iterator
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GR16Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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if (RI->hasFP(MF))
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return X86_GR16_AO_64_fp;
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else
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return X86_GR16_AO_64;
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} else {
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if (RI->hasFP(MF))
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return X86_GR16_AO_32_fp;
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else
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return X86_GR16_AO_32;
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}
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if (Subtarget.is64Bit())
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return X86_GR16_AO_64;
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else
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return begin();
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}
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GR16Class::iterator
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@ -377,15 +344,21 @@ def GR16 : RegisterClass<"X86", [i16], 16,
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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// Does the function dedicate RBP to being a frame ptr?
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if (RI->hasFP(MF))
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return array_endof(X86_GR16_AO_64_fp);
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// If so, don't allocate SP or BP.
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return array_endof(X86_GR16_AO_64) - 1;
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else
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// If not, just don't allocate SP.
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return array_endof(X86_GR16_AO_64);
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} else {
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// Does the function dedicate EBP to being a frame ptr?
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if (RI->hasFP(MF))
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return array_endof(X86_GR16_AO_32_fp);
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// If so, don't allocate SP or BP.
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return begin() + 6;
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else
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return array_endof(X86_GR16_AO_32);
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// If not, just don't allocate SP.
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return begin() + 7;
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}
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}
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}];
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@ -401,42 +374,20 @@ def GR32 : RegisterClass<"X86", [i32], 32,
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate ESP or EBP.
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static const unsigned X86_GR32_AO_64_fp[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
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X86::R8D, X86::R9D, X86::R10D, X86::R11D,
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X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D
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};
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static const unsigned X86_GR32_AO_32_fp[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX
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};
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// If not, just don't allocate ESP.
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static const unsigned X86_GR32_AO_64[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
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X86::R8D, X86::R9D, X86::R10D, X86::R11D,
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X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
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};
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static const unsigned X86_GR32_AO_32[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP
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};
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GR32Class::iterator
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GR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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if (RI->hasFP(MF))
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return X86_GR32_AO_64_fp;
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else
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return X86_GR32_AO_64;
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} else {
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if (RI->hasFP(MF))
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return X86_GR32_AO_32_fp;
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else
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return X86_GR32_AO_32;
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}
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if (Subtarget.is64Bit())
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return X86_GR32_AO_64;
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else
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return begin();
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}
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GR32Class::iterator
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@ -445,15 +396,21 @@ def GR32 : RegisterClass<"X86", [i32], 32,
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit()) {
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// Does the function dedicate RBP to being a frame ptr?
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if (RI->hasFP(MF))
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return array_endof(X86_GR32_AO_64_fp);
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// If so, don't allocate ESP or EBP.
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return array_endof(X86_GR32_AO_64) - 1;
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else
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// If not, just don't allocate ESP.
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return array_endof(X86_GR32_AO_64);
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} else {
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// Does the function dedicate EBP to being a frame ptr?
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if (RI->hasFP(MF))
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return array_endof(X86_GR32_AO_32_fp);
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// If so, don't allocate ESP or EBP.
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return begin() + 6;
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else
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return array_endof(X86_GR32_AO_32);
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// If not, just don't allocate ESP.
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return begin() + 7;
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}
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}
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}];
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@ -509,38 +466,25 @@ def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
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// On x86-64, GR64_NOREX, GR32_NOREX and GR16_NOREX are the classes
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// of registers which do not by themselves require a REX prefix.
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def GR8_NOREX : RegisterClass<"X86", [i8], 8,
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[AL, CL, DL, BL, AH, CH, DH, BH,
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[AL, CL, DL, AH, CH, DH, BL, BH,
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SIL, DIL, BPL, SPL]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate SPL or BPL.
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static const unsigned X86_GR8_NOREX_AO_64_fp[] = {
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X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL
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};
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// If not, just don't allocate SPL.
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static const unsigned X86_GR8_NOREX_AO_64[] = {
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X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
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};
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// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
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static const unsigned X86_GR8_NOREX_AO_32[] = {
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X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH
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};
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GR8_NOREXClass::iterator
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GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (!Subtarget.is64Bit())
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return X86_GR8_NOREX_AO_32;
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else if (RI->hasFP(MF))
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return X86_GR8_NOREX_AO_64_fp;
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else
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if (Subtarget.is64Bit())
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return X86_GR8_NOREX_AO_64;
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else
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return begin();
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}
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GR8_NOREXClass::iterator
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@ -548,11 +492,15 @@ def GR8_NOREX : RegisterClass<"X86", [i8], 8,
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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// Does the function dedicate RBP / EBP to being a frame ptr?
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if (!Subtarget.is64Bit())
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return array_endof(X86_GR8_NOREX_AO_32);
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// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
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return begin() + 8;
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else if (RI->hasFP(MF))
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return array_endof(X86_GR8_NOREX_AO_64_fp);
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// If so, don't allocate SPL or BPL.
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return array_endof(X86_GR8_NOREX_AO_64) - 1;
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else
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// If not, just don't allocate SPL.
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return array_endof(X86_GR8_NOREX_AO_64);
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}
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}];
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@ -561,38 +509,20 @@ def GR16_NOREX : RegisterClass<"X86", [i16], 16,
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[AX, CX, DX, SI, DI, BX, BP, SP]> {
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let SubRegClassList = [GR8_NOREX, GR8_NOREX];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate SP or BP.
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static const unsigned X86_GR16_AO_fp[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX
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};
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// If not, just don't allocate SP.
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static const unsigned X86_GR16_AO[] = {
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X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP
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};
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GR16_NOREXClass::iterator
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GR16_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return X86_GR16_AO_fp;
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else
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return X86_GR16_AO;
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}
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GR16_NOREXClass::iterator
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GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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// Does the function dedicate RBP / EBP to being a frame ptr?
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if (RI->hasFP(MF))
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return array_endof(X86_GR16_AO_fp);
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// If so, don't allocate SP or BP.
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return end() - 2;
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else
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return array_endof(X86_GR16_AO);
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// If not, just don't allocate SP.
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return end() - 1;
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}
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}];
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}
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@ -601,38 +531,20 @@ def GR32_NOREX : RegisterClass<"X86", [i32], 32,
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[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
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let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate ESP or EBP.
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static const unsigned X86_GR32_NOREX_AO_fp[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX
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};
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// If not, just don't allocate ESP.
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static const unsigned X86_GR32_NOREX_AO[] = {
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X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP
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};
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GR32_NOREXClass::iterator
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GR32_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return X86_GR32_NOREX_AO_fp;
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else
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return X86_GR32_NOREX_AO;
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}
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GR32_NOREXClass::iterator
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GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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// Does the function dedicate RBP / EBP to being a frame ptr?
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if (RI->hasFP(MF))
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return array_endof(X86_GR32_NOREX_AO_fp);
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// If so, don't allocate ESP or EBP.
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return end() - 2;
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else
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return array_endof(X86_GR32_NOREX_AO);
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// If not, just don't allocate ESP.
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return end() - 1;
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}
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}];
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}
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@ -642,38 +554,20 @@ def GR64_NOREX : RegisterClass<"X86", [i64], 64,
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[RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP]> {
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let SubRegClassList = [GR8_NOREX, GR8_NOREX, GR16_NOREX, GR32_NOREX];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// Does the function dedicate RBP / EBP to being a frame ptr?
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// If so, don't allocate RSP or RBP.
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static const unsigned X86_GR64_NOREX_AO_fp[] = {
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X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX
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};
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// If not, just don't allocate RSP.
|
||||
static const unsigned X86_GR64_NOREX_AO[] = {
|
||||
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP
|
||||
};
|
||||
|
||||
GR64_NOREXClass::iterator
|
||||
GR64_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
||||
if (RI->hasFP(MF))
|
||||
return X86_GR64_NOREX_AO_fp;
|
||||
else
|
||||
return X86_GR64_NOREX_AO;
|
||||
}
|
||||
|
||||
GR64_NOREXClass::iterator
|
||||
GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
||||
// Does the function dedicate RBP / EBP to being a frame ptr?
|
||||
if (RI->hasFP(MF))
|
||||
return array_endof(X86_GR64_NOREX_AO_fp);
|
||||
// If so, don't allocate RSP or RBP.
|
||||
return end() - 2;
|
||||
else
|
||||
return array_endof(X86_GR64_NOREX_AO);
|
||||
// If not, just don't allocate RSP.
|
||||
return end() - 1;
|
||||
}
|
||||
}];
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user