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Replace the LiveRegs SmallSet with a simple counter that keeps
track of the number of live registers, which is all the set was being used for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56498 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,7 +39,7 @@ namespace {
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/// all nodes to have the same priority.
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///
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struct VISIBILITY_HIDDEN FastPriorityQueue {
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std::vector<SUnit *> Queue;
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SmallVector<SUnit *, 16> Queue;
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bool empty() const { return Queue.empty(); }
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@ -63,10 +63,10 @@ private:
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/// AvailableQueue - The priority queue to use for the available SUnits.
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FastPriorityQueue AvailableQueue;
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/// LiveRegs / LiveRegDefs - A set of physical registers and their definition
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/// LiveRegDefs - A set of physical registers and their definition
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/// that are "live". These nodes must be scheduled before any other nodes that
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/// modifies the registers can be scheduled.
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SmallSet<unsigned, 4> LiveRegs;
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unsigned NumLiveRegs;
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std::vector<SUnit*> LiveRegDefs;
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std::vector<unsigned> LiveRegCycles;
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@ -117,6 +117,7 @@ private:
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void ScheduleDAGFast::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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NumLiveRegs = 0;
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegCycles.resize(TRI->getNumRegs(), 0);
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@ -178,7 +179,8 @@ void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (LiveRegs.insert(I->Reg)) {
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if (!LiveRegDefs[I->Reg]) {
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++NumLiveRegs;
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LiveRegDefs[I->Reg] = I->Dep;
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LiveRegCycles[I->Reg] = CurCycle;
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}
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@ -190,9 +192,10 @@ void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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I != E; ++I) {
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if (I->Cost < 0) {
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if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
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LiveRegs.erase(I->Reg);
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assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
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assert(LiveRegDefs[I->Reg] == SU &&
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"Physical register dependency violated?");
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--NumLiveRegs;
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LiveRegDefs[I->Reg] = NULL;
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LiveRegCycles[I->Reg] = 0;
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}
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@ -460,7 +463,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
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/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
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bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
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SmallVector<unsigned, 4> &LRegs){
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if (LiveRegs.empty())
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if (NumLiveRegs == 0)
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return false;
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SmallSet<unsigned, 4> RegAdded;
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@ -469,13 +472,13 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
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I != E; ++I) {
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if (I->Cost < 0) {
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unsigned Reg = I->Reg;
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if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
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if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
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if (RegAdded.insert(Reg))
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LRegs.push_back(Reg);
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg);
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*Alias; ++Alias)
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if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
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if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
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if (RegAdded.insert(*Alias))
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LRegs.push_back(*Alias);
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}
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@ -490,13 +493,13 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
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if (!TID.ImplicitDefs)
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continue;
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for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
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if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
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if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) {
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if (RegAdded.insert(*Reg))
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LRegs.push_back(*Reg);
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}
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for (const unsigned *Alias = TRI->getAliasSet(*Reg);
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*Alias; ++Alias)
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if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
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if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
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if (RegAdded.insert(*Alias))
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LRegs.push_back(*Alias);
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}
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@ -66,10 +66,10 @@ private:
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/// AvailableQueue - The priority queue to use for the available SUnits.
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SchedulingPriorityQueue *AvailableQueue;
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/// LiveRegs / LiveRegDefs - A set of physical registers and their definition
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/// LiveRegDefs - A set of physical registers and their definition
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/// that are "live". These nodes must be scheduled before any other nodes that
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/// modifies the registers can be scheduled.
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SmallSet<unsigned, 4> LiveRegs;
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unsigned NumLiveRegs;
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std::vector<SUnit*> LiveRegDefs;
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std::vector<unsigned> LiveRegCycles;
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@ -178,6 +178,7 @@ private:
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void ScheduleDAGRRList::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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NumLiveRegs = 0;
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegCycles.resize(TRI->getNumRegs(), 0);
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@ -308,7 +309,8 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (LiveRegs.insert(I->Reg)) {
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if (!LiveRegDefs[I->Reg]) {
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++NumLiveRegs;
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LiveRegDefs[I->Reg] = I->Dep;
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LiveRegCycles[I->Reg] = CurCycle;
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}
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@ -320,9 +322,10 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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I != E; ++I) {
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if (I->Cost < 0) {
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if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
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LiveRegs.erase(I->Reg);
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assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
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assert(LiveRegDefs[I->Reg] == SU &&
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"Physical register dependency violated?");
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--NumLiveRegs;
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LiveRegDefs[I->Reg] = NULL;
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LiveRegCycles[I->Reg] = 0;
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}
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@ -367,9 +370,10 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
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I != E; ++I) {
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CapturePred(I->Dep, SU, I->isCtrl);
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if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
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LiveRegs.erase(I->Reg);
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assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
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assert(LiveRegDefs[I->Reg] == I->Dep &&
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"Physical register dependency violated?");
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--NumLiveRegs;
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LiveRegDefs[I->Reg] = NULL;
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LiveRegCycles[I->Reg] = 0;
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}
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@ -378,10 +382,9 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->Cost < 0) {
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if (LiveRegs.insert(I->Reg)) {
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assert(!LiveRegDefs[I->Reg] &&
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"Physical register dependency violated?");
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if (!LiveRegDefs[I->Reg]) {
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LiveRegDefs[I->Reg] = SU;
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++NumLiveRegs;
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}
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if (I->Dep->Cycle < LiveRegCycles[I->Reg])
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LiveRegCycles[I->Reg] = I->Dep->Cycle;
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@ -878,7 +881,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
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/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
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bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
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SmallVector<unsigned, 4> &LRegs){
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if (LiveRegs.empty())
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if (NumLiveRegs == 0)
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return false;
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SmallSet<unsigned, 4> RegAdded;
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@ -887,13 +890,13 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
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I != E; ++I) {
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if (I->Cost < 0) {
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unsigned Reg = I->Reg;
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if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
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if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
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if (RegAdded.insert(Reg))
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LRegs.push_back(Reg);
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg);
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*Alias; ++Alias)
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if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
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if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
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if (RegAdded.insert(*Alias))
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LRegs.push_back(*Alias);
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}
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@ -908,13 +911,13 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
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if (!TID.ImplicitDefs)
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continue;
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for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
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if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
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if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) {
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if (RegAdded.insert(*Reg))
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LRegs.push_back(*Reg);
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}
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for (const unsigned *Alias = TRI->getAliasSet(*Reg);
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*Alias; ++Alias)
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if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
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if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
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if (RegAdded.insert(*Alias))
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LRegs.push_back(*Alias);
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}
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