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Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but in order to use the r+i forms, the offset must be a multiple of 4. Unfortunately, this cannot always be determined by examining the immediate itself because it might be available only via a TOC entry. In order to get around this issue, we additionally predicate the selection of the r+i form on the alignment of the load or store (forcing it to be at least 4 in order to select the r+i form). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
bf37bf9e21
commit
08a215c286
@ -1183,13 +1183,15 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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SDValue Ptr;
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EVT VT;
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unsigned Alignment;
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
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Ptr = LD->getBasePtr();
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VT = LD->getMemoryVT();
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Alignment = LD->getAlignment();
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} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
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Ptr = ST->getBasePtr();
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VT = ST->getMemoryVT();
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Alignment = ST->getAlignment();
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} else
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return false;
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@ -1208,6 +1210,10 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
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return false;
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} else {
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// LDU/STU need an address with at least 4-byte alignment.
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if (Alignment < 4)
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return false;
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// reg + imm * 4.
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if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
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return false;
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@ -555,7 +555,8 @@ def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
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PPC970_DGroup_Cracked;
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def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
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"lwa $rD, $src", LdStLWA,
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[(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
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[(set G8RC:$rD,
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(aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
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PPC970_DGroup_Cracked;
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def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
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"lhax $rD, $src", LdStLHA,
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@ -648,7 +649,7 @@ def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc:$ea_result),
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let canFoldAsLoad = 1, PPC970_Unit = 2 in {
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def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
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"ld $rD, $src", LdStLD,
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[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
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[(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
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def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src),
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"ld $rD, $src", LdStLD,
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[]>, isPPC64;
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@ -682,6 +683,10 @@ def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
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def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
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"ldx $rD, $src", LdStLD,
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[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
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let isCodeGenOnly = 1 in
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def LDXu : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
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"ldx $rD, $src", LdStLD,
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[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
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let mayLoad = 1 in
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def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
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@ -798,7 +803,7 @@ def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
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// Normal 8-byte stores.
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def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
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"std $rS, $dst", LdStSTD,
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[(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
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[(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
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def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
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"stdx $rS, $dst", LdStSTD,
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[(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
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@ -833,8 +838,9 @@ def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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s16immX4:$ptroff, ptr_rc:$ptrreg),
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"stdu $rS, $ptroff($ptrreg)", LdStSTDU,
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[(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
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iaddroff:$ptroff))]>,
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[(set ptr_rc:$ea_res,
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(aligned4pre_store G8RC:$rS, ptr_rc:$ptrreg,
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iaddroff:$ptroff))]>,
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RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
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isPPC64;
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@ -979,3 +985,13 @@ def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
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(ADDIS8 G8RC:$in, tjumptable:$g)>;
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def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
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(ADDIS8 G8RC:$in, tblockaddress:$g)>;
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// Patterns to match r+r indexed loads and stores for
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// addresses without at least 4-byte alignment.
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def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
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(LWAX xoaddr:$src)>;
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def : Pat<(i64 (unaligned4load xoaddr:$src)),
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(LDX xoaddr:$src)>;
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def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst),
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(STDX G8RC:$rS, xoaddr:$dst)>;
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@ -278,6 +278,38 @@ def imm16ShiftedSExt : PatLeaf<(imm), [{
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return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
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}], HI16>;
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// Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
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// restricted memrix (offset/4) constants are alignment sensitive. If these
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// offsets are hidden behind TOC entries than the values of the lower-order
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// bits cannot be checked directly. As a result, we need to also incorporate
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// an alignment check into the relevant patterns.
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def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 4;
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}]>;
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def aligned4store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return cast<StoreSDNode>(N)->getAlignment() >= 4;
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}]>;
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def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 4;
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}]>;
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def aligned4pre_store : PatFrag<
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(ops node:$val, node:$base, node:$offset),
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(pre_store node:$val, node:$base, node:$offset), [{
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return cast<StoreSDNode>(N)->getAlignment() >= 4;
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}]>;
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def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() < 4;
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}]>;
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def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return cast<StoreSDNode>(N)->getAlignment() < 4;
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}]>;
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def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() < 4;
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}]>;
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//===----------------------------------------------------------------------===//
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// PowerPC Flag Definitions.
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24
test/CodeGen/PowerPC/unal4-std.ll
Normal file
24
test/CodeGen/PowerPC/unal4-std.ll
Normal file
@ -0,0 +1,24 @@
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; RUN: llc < %s -mcpu=pwr7 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define fastcc void @copy_to_conceal() #0 {
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entry:
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br i1 undef, label %if.then, label %if.end210
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if.then: ; preds = %entry
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br label %vector.body.i
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vector.body.i: ; preds = %vector.body.i, %if.then
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%index.i = phi i64 [ 0, %vector.body.i ], [ 0, %if.then ]
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store <8 x i16> zeroinitializer, <8 x i16>* undef, align 2
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br label %vector.body.i
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if.end210: ; preds = %entry
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ret void
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; CHECK: @copy_to_conceal
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; CHECK: stdx {{[0-9]+}}, 0,
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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