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08a215c286
PPC64 supports unaligned loads and stores of 64-bit values, but in order to use the r+i forms, the offset must be a multiple of 4. Unfortunately, this cannot always be determined by examining the immediate itself because it might be available only via a TOC entry. In order to get around this issue, we additionally predicate the selection of the r+i form on the alignment of the load or store (forcing it to be at least 4 in order to select the r+i form). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1016 B
LLVM
25 lines
1016 B
LLVM
; RUN: llc < %s -mcpu=pwr7 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define fastcc void @copy_to_conceal() #0 {
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entry:
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br i1 undef, label %if.then, label %if.end210
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if.then: ; preds = %entry
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br label %vector.body.i
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vector.body.i: ; preds = %vector.body.i, %if.then
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%index.i = phi i64 [ 0, %vector.body.i ], [ 0, %if.then ]
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store <8 x i16> zeroinitializer, <8 x i16>* undef, align 2
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br label %vector.body.i
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if.end210: ; preds = %entry
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ret void
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; CHECK: @copy_to_conceal
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; CHECK: stdx {{[0-9]+}}, 0,
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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