mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Clang-format over X86AsmInstrumentation.*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216536 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evgeniy Stepanov
parent
e79a94a839
commit
08cb02e91a
@ -42,33 +42,35 @@ std::string FuncName(unsigned AccessSize, bool IsWrite) {
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}
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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public:
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X86AddressSanitizer(const MCSubtargetInfo &STI)
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: X86AsmInstrumentation(STI), RepPrefix(false) {}
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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virtual void InstrumentAndEmitInstruction(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) override {
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virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
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OperandVector &Operands,
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MCContext &Ctx,
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const MCInstrInfo &MII,
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MCStreamer &Out) override {
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InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
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if (RepPrefix)
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EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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if (RepPrefix) EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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InstrumentMOV(Inst, Operands, Ctx, MII, Out);
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RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
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if (!RepPrefix)
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EmitInstruction(Out, Inst);
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if (!RepPrefix) EmitInstruction(Out, Inst);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) = 0;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) = 0;
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@ -83,14 +85,15 @@ public:
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void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
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protected:
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protected:
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// True when previous instruction was actually REP prefix.
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bool RepPrefix;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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MCParsedAsmOperand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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void X86AddressSanitizer::InstrumentMemOperand(MCParsedAsmOperand &Op,
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unsigned AccessSize,
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bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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assert(Op.isMem() && "Op should be a memory operand.");
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assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
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"AccessSize should be a power of two, less or equal than 16.");
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@ -107,9 +110,10 @@ void X86AddressSanitizer::InstrumentMemOperand(
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InstrumentMemOperandLargeImpl(MemOp, AccessSize, IsWrite, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOVSBase(
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unsigned DstReg, unsigned SrcReg, unsigned CntReg, unsigned AccessSize,
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MCContext &Ctx, MCStreamer &Out) {
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void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
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unsigned CntReg,
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unsigned AccessSize,
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MCContext &Ctx, MCStreamer &Out) {
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// FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
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// and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
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@ -149,92 +153,95 @@ void X86AddressSanitizer::InstrumentMOVSBase(
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}
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}
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void X86AddressSanitizer::InstrumentMOVS(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) {
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void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
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OperandVector &Operands,
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MCContext &Ctx, const MCInstrInfo &MII,
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MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOVSB:
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AccessSize = 1;
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break;
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case X86::MOVSW:
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AccessSize = 2;
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break;
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case X86::MOVSL:
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AccessSize = 4;
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break;
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case X86::MOVSQ:
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AccessSize = 8;
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break;
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default:
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return;
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case X86::MOVSB:
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AccessSize = 1;
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break;
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case X86::MOVSW:
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AccessSize = 2;
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break;
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case X86::MOVSL:
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AccessSize = 4;
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break;
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case X86::MOVSQ:
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AccessSize = 8;
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break;
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default:
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return;
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}
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InstrumentMOVSImpl(AccessSize, Ctx, Out);
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}
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void X86AddressSanitizer::InstrumentMOV(
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const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII, MCStreamer &Out) {
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void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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OperandVector &Operands, MCContext &Ctx,
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const MCInstrInfo &MII,
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MCStreamer &Out) {
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// Access size in bytes.
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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}
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const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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assert(Operands[Ix]);
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem())
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InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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if (Op.isMem()) InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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}
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}
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class X86AddressSanitizer32 : public X86AddressSanitizer {
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public:
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public:
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static const long kShadowOffset = 0x20000000;
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X86AddressSanitizer32(const MCSubtargetInfo &STI)
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer32() {}
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) override;
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@ -244,8 +251,10 @@ public:
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::ESP)
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.addReg(X86::ESP).addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
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.addReg(X86::ESP)
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.addReg(X86::ESP)
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.addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(AddressReg));
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const std::string &Fn = FuncName(AccessSize, IsWrite);
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@ -256,9 +265,11 @@ public:
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}
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};
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void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EDX));
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@ -274,8 +285,9 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
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{
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MCInst Inst;
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@ -296,31 +308,34 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EDX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::EDX)
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.addReg(X86::EDX).addImm(7));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7));
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switch (AccessSize) {
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EDX));
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EDX));
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::EDX)
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.addReg(X86::EDX).addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::EDX)
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.addReg(X86::EDX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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EmitInstruction(
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@ -338,9 +353,11 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(X86::ECX));
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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@ -354,8 +371,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EAX));
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EmitInstruction(Out, MCInstBuilder(X86::SHR32ri).addReg(X86::ECX)
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.addReg(X86::ECX).addImm(3));
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EmitInstruction(
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Out,
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MCInstBuilder(X86::SHR32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(3));
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{
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MCInst Inst;
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switch (AccessSize) {
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@ -388,8 +406,9 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(X86::EAX));
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}
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void X86AddressSanitizer32::InstrumentMOVSImpl(
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unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) {
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void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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// No need to test when ECX is equals to zero.
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@ -408,23 +427,25 @@ void X86AddressSanitizer32::InstrumentMOVSImpl(
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}
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class X86AddressSanitizer64 : public X86AddressSanitizer {
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public:
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public:
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static const long kShadowOffset = 0x7fff8000;
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X86AddressSanitizer64(const MCSubtargetInfo &STI)
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: X86AddressSanitizer(STI) {}
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virtual ~X86AddressSanitizer64() {}
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virtual void InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMemOperandLargeImpl(X86Operand &Op,
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unsigned AccessSize, bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) override;
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) override;
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private:
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private:
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void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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@ -442,8 +463,10 @@ private:
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP)
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.addReg(X86::RSP).addImm(-16));
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EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
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.addReg(X86::RSP)
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.addReg(X86::RSP)
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.addImm(-16));
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const std::string &Fn = FuncName(AccessSize, IsWrite);
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MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
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@ -453,9 +476,11 @@ private:
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}
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};
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void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
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X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
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MCStreamer &Out) {
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void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op,
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unsigned AccessSize,
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bool IsWrite,
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MCContext &Ctx,
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MCStreamer &Out) {
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EmitAdjustRSP(Ctx, Out, -128);
|
||||
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
|
||||
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RCX));
|
||||
@ -470,8 +495,9 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
|
||||
}
|
||||
EmitInstruction(
|
||||
Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RAX).addReg(X86::RDI));
|
||||
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
|
||||
.addReg(X86::RAX).addImm(3));
|
||||
EmitInstruction(
|
||||
Out,
|
||||
MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
|
||||
{
|
||||
MCInst Inst;
|
||||
Inst.setOpcode(X86::MOV8rm);
|
||||
@ -491,31 +517,34 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
|
||||
|
||||
EmitInstruction(
|
||||
Out, MCInstBuilder(X86::MOV32rr).addReg(X86::ECX).addReg(X86::EDI));
|
||||
EmitInstruction(Out, MCInstBuilder(X86::AND32ri).addReg(X86::ECX)
|
||||
.addReg(X86::ECX).addImm(7));
|
||||
EmitInstruction(
|
||||
Out,
|
||||
MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7));
|
||||
|
||||
switch (AccessSize) {
|
||||
case 1:
|
||||
break;
|
||||
case 2: {
|
||||
MCInst Inst;
|
||||
Inst.setOpcode(X86::LEA32r);
|
||||
Inst.addOperand(MCOperand::CreateReg(X86::ECX));
|
||||
case 1:
|
||||
break;
|
||||
case 2: {
|
||||
MCInst Inst;
|
||||
Inst.setOpcode(X86::LEA32r);
|
||||
Inst.addOperand(MCOperand::CreateReg(X86::ECX));
|
||||
|
||||
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
|
||||
std::unique_ptr<X86Operand> Op(
|
||||
X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
|
||||
Op->addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
break;
|
||||
}
|
||||
case 4:
|
||||
EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8).addReg(X86::ECX)
|
||||
.addReg(X86::ECX).addImm(3));
|
||||
break;
|
||||
default:
|
||||
assert(false && "Incorrect access size");
|
||||
break;
|
||||
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
|
||||
std::unique_ptr<X86Operand> Op(
|
||||
X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
|
||||
Op->addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
break;
|
||||
}
|
||||
case 4:
|
||||
EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
|
||||
.addReg(X86::ECX)
|
||||
.addReg(X86::ECX)
|
||||
.addImm(3));
|
||||
break;
|
||||
default:
|
||||
assert(false && "Incorrect access size");
|
||||
break;
|
||||
}
|
||||
|
||||
EmitInstruction(
|
||||
@ -534,9 +563,11 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(
|
||||
EmitAdjustRSP(Ctx, Out, 128);
|
||||
}
|
||||
|
||||
void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
|
||||
X86Operand &Op, unsigned AccessSize, bool IsWrite, MCContext &Ctx,
|
||||
MCStreamer &Out) {
|
||||
void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op,
|
||||
unsigned AccessSize,
|
||||
bool IsWrite,
|
||||
MCContext &Ctx,
|
||||
MCStreamer &Out) {
|
||||
EmitAdjustRSP(Ctx, Out, -128);
|
||||
EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RAX));
|
||||
EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
|
||||
@ -548,20 +579,21 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
|
||||
Op.addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
}
|
||||
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri).addReg(X86::RAX)
|
||||
.addReg(X86::RAX).addImm(3));
|
||||
EmitInstruction(
|
||||
Out,
|
||||
MCInstBuilder(X86::SHR64ri).addReg(X86::RAX).addReg(X86::RAX).addImm(3));
|
||||
{
|
||||
MCInst Inst;
|
||||
switch (AccessSize) {
|
||||
case 8:
|
||||
Inst.setOpcode(X86::CMP8mi);
|
||||
break;
|
||||
case 16:
|
||||
Inst.setOpcode(X86::CMP16mi);
|
||||
break;
|
||||
default:
|
||||
assert(false && "Incorrect access size");
|
||||
break;
|
||||
case 8:
|
||||
Inst.setOpcode(X86::CMP8mi);
|
||||
break;
|
||||
case 16:
|
||||
Inst.setOpcode(X86::CMP16mi);
|
||||
break;
|
||||
default:
|
||||
assert(false && "Incorrect access size");
|
||||
break;
|
||||
}
|
||||
const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
|
||||
std::unique_ptr<X86Operand> Op(
|
||||
@ -583,8 +615,9 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(
|
||||
EmitAdjustRSP(Ctx, Out, 128);
|
||||
}
|
||||
|
||||
void X86AddressSanitizer64::InstrumentMOVSImpl(
|
||||
unsigned AccessSize, MCContext &Ctx, MCStreamer &Out) {
|
||||
void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
|
||||
MCContext &Ctx,
|
||||
MCStreamer &Out) {
|
||||
EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
|
||||
|
||||
// No need to test when RCX is equals to zero.
|
||||
@ -602,7 +635,7 @@ void X86AddressSanitizer64::InstrumentMOVSImpl(
|
||||
EmitInstruction(Out, MCInstBuilder(X86::POPF64));
|
||||
}
|
||||
|
||||
} // End anonymous namespace
|
||||
} // End anonymous namespace
|
||||
|
||||
X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
|
||||
: STI(STI) {}
|
||||
@ -620,9 +653,9 @@ void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
|
||||
Out.EmitInstruction(Inst, STI);
|
||||
}
|
||||
|
||||
X86AsmInstrumentation *
|
||||
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
|
||||
const MCContext &Ctx, const MCSubtargetInfo &STI) {
|
||||
X86AsmInstrumentation *CreateX86AsmInstrumentation(
|
||||
const MCTargetOptions &MCOptions, const MCContext &Ctx,
|
||||
const MCSubtargetInfo &STI) {
|
||||
Triple T(STI.getTargetTriple());
|
||||
const bool hasCompilerRTSupport = T.isOSLinux();
|
||||
if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
|
||||
@ -635,4 +668,4 @@ CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
|
||||
return new X86AsmInstrumentation(STI);
|
||||
}
|
||||
|
||||
} // End llvm namespace
|
||||
} // End llvm namespace
|
||||
|
||||
@ -26,12 +26,12 @@ class MCTargetOptions;
|
||||
|
||||
class X86AsmInstrumentation;
|
||||
|
||||
X86AsmInstrumentation *
|
||||
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
|
||||
const MCContext &Ctx, const MCSubtargetInfo &STI);
|
||||
X86AsmInstrumentation *CreateX86AsmInstrumentation(
|
||||
const MCTargetOptions &MCOptions, const MCContext &Ctx,
|
||||
const MCSubtargetInfo &STI);
|
||||
|
||||
class X86AsmInstrumentation {
|
||||
public:
|
||||
public:
|
||||
virtual ~X86AsmInstrumentation();
|
||||
|
||||
// Tries to instrument and emit instruction.
|
||||
@ -40,10 +40,10 @@ public:
|
||||
SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> &Operands,
|
||||
MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
|
||||
|
||||
protected:
|
||||
friend X86AsmInstrumentation *
|
||||
CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
|
||||
const MCContext &Ctx, const MCSubtargetInfo &STI);
|
||||
protected:
|
||||
friend X86AsmInstrumentation *CreateX86AsmInstrumentation(
|
||||
const MCTargetOptions &MCOptions, const MCContext &Ctx,
|
||||
const MCSubtargetInfo &STI);
|
||||
|
||||
X86AsmInstrumentation(const MCSubtargetInfo &STI);
|
||||
|
||||
@ -52,6 +52,6 @@ protected:
|
||||
const MCSubtargetInfo &STI;
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
} // End llvm namespace
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user