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[NVPTX] Add more precise PTX/SM target attributes

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Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally,
PTX 3.1 is added as the default PTX version to be out-of-the-box compatible
with CUDA 5.0.

Available CPUs for this target:

  sm_10 - Select the sm_10 processor.
  sm_11 - Select the sm_11 processor.
  sm_12 - Select the sm_12 processor.
  sm_13 - Select the sm_13 processor.
  sm_20 - Select the sm_20 processor.
  sm_21 - Select the sm_21 processor.
  sm_30 - Select the sm_30 processor.
  sm_35 - Select the sm_35 processor.

Available features for this target:

  ptx30 - Use PTX version 3.0.
  ptx31 - Use PTX version 3.1.
  sm_10 - Target SM 1.0.
  sm_11 - Target SM 1.1.
  sm_12 - Target SM 1.2.
  sm_13 - Target SM 1.3.
  sm_20 - Target SM 2.0.
  sm_21 - Target SM 2.1.
  sm_30 - Target SM 3.0.
  sm_35 - Target SM 3.5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski 2012-11-12 03:16:43 +00:00
parent b798edd791
commit 08e9cb46fe
14 changed files with 117 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Target/NVPTX/NVPTX.td
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@ -24,7 +24,30 @@ include "NVPTXInstrInfo.td"
// - Need at least one feature to avoid generating zero sized array by
// TableGen in NVPTXGenSubtarget.inc.
//===----------------------------------------------------------------------===//
def FeatureDummy : SubtargetFeature<"dummy", "dummy", "true", "">;
// SM Versions
def SM10 : SubtargetFeature<"sm_10", "SmVersion", "10",
"Target SM 1.0">;
def SM11 : SubtargetFeature<"sm_11", "SmVersion", "11",
"Target SM 1.1">;
def SM12 : SubtargetFeature<"sm_12", "SmVersion", "12",
"Target SM 1.2">;
def SM13 : SubtargetFeature<"sm_13", "SmVersion", "13",
"Target SM 1.3">;
def SM20 : SubtargetFeature<"sm_20", "SmVersion", "20",
"Target SM 2.0">;
def SM21 : SubtargetFeature<"sm_21", "SmVersion", "21",
"Target SM 2.1">;
def SM30 : SubtargetFeature<"sm_30", "SmVersion", "30",
"Target SM 3.0">;
def SM35 : SubtargetFeature<"sm_35", "SmVersion", "35",
"Target SM 3.5">;
// PTX Versions
def PTX30 : SubtargetFeature<"ptx30", "PTXVersion", "30",
"Use PTX version 3.0">;
def PTX31 : SubtargetFeature<"ptx31", "PTXVersion", "31",
"Use PTX version 3.1">;
//===----------------------------------------------------------------------===//
// NVPTX supported processors.
@ -33,7 +56,14 @@ def FeatureDummy : SubtargetFeature<"dummy", "dummy", "true", "">;
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Proc<"sm_10", [FeatureDummy]>;
def : Proc<"sm_10", [SM10]>;
def : Proc<"sm_11", [SM11]>;
def : Proc<"sm_12", [SM12]>;
def : Proc<"sm_13", [SM13]>;
def : Proc<"sm_20", [SM20]>;
def : Proc<"sm_21", [SM21]>;
def : Proc<"sm_30", [SM30]>;
def : Proc<"sm_35", [SM35]>;
def NVPTXInstrInfo : InstrInfo {

3
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
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@ -910,7 +910,8 @@ void NVPTXAsmPrinter::emitHeader (Module &M, raw_ostream &O) {
O << "//\n";
O << "\n";
O << ".version 3.0\n";
unsigned PTXVersion = nvptxSubtarget.getPTXVersion();
O << ".version " << (PTXVersion / 10) << "." << (PTXVersion % 10) << "\n";
O << ".target ";
O << nvptxSubtarget.getTargetName();

20
lib/Target/NVPTX/NVPTXSubtarget.cpp
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@ -34,16 +34,18 @@ DriverInterface(cl::desc("Choose driver interface:"),
NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool is64Bit)
:NVPTXGenSubtargetInfo(TT, "", FS), // Don't pass CPU to subtarget,
// because we don't register all
// nvptx targets.
Is64Bit(is64Bit) {
: NVPTXGenSubtargetInfo(TT, CPU, FS),
Is64Bit(is64Bit),
PTXVersion(0),
SmVersion(10) {
drvInterface = DriverInterface;
// Provide the default CPU if none
std::string defCPU = "sm_10";
ParseSubtargetFeatures((CPU.empty() ? defCPU : CPU), FS);
// Get the TargetName from the FS if available
if (FS.empty() && CPU.empty())
TargetName = defCPU;
@ -52,6 +54,12 @@ NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
else
llvm_unreachable("we are not using FeatureStr");
// Set up the SmVersion
SmVersion = atoi(TargetName.c_str()+3);
// We default to PTX 3.1, but we cannot just default to it in the initializer
// since the attribute parser checks if the given option is >= the default.
// So if we set ptx31 as the default, the ptx30 attribute would never match.
// Instead, we use 0 as the default and manually set 31 if the default is
// used.
if (PTXVersion == 0) {
PTXVersion = 31;
}
}

11
lib/Target/NVPTX/NVPTXSubtarget.h
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@ -25,13 +25,18 @@
namespace llvm {
class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
unsigned int SmVersion;
std::string TargetName;
NVPTX::DrvInterface drvInterface;
bool dummy; // For the 'dummy' feature, see NVPTX.td
bool Is64Bit;
// PTX version x.y is represented as 10*x+y, e.g. 3.1 == 31
unsigned PTXVersion;
// SM version x.y is represented as 10*x+y, e.g. 3.1 == 31
unsigned int SmVersion;
public:
/// This constructor initializes the data members to match that
/// of the specified module.
@ -69,6 +74,8 @@ public:
NVPTX::DrvInterface getDrvInterface() const { return drvInterface; }
std::string getTargetName() const { return TargetName; }
unsigned getPTXVersion() const { return PTXVersion; }
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
std::string getDataLayout() const {

6
test/CodeGen/NVPTX/ptx-version-30.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -mattr=ptx30 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -mattr=ptx30 | FileCheck %s
; CHECK: .version 3.0

6
test/CodeGen/NVPTX/ptx-version-31.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -mattr=ptx31 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -mattr=ptx31 | FileCheck %s
; CHECK: .version 3.1

6
test/CodeGen/NVPTX/sm-version-10.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
; CHECK: .target sm_10

6
test/CodeGen/NVPTX/sm-version-11.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_11 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_11 | FileCheck %s
; CHECK: .target sm_11

6
test/CodeGen/NVPTX/sm-version-12.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_12 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_12 | FileCheck %s
; CHECK: .target sm_12

6
test/CodeGen/NVPTX/sm-version-13.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_13 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_13 | FileCheck %s
; CHECK: .target sm_13

6
test/CodeGen/NVPTX/sm-version-20.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
; CHECK: .target sm_20

6
test/CodeGen/NVPTX/sm-version-21.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_21 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_21 | FileCheck %s
; CHECK: .target sm_21

6
test/CodeGen/NVPTX/sm-version-30.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 | FileCheck %s
; CHECK: .target sm_30

6
test/CodeGen/NVPTX/sm-version-35.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
; CHECK: .target sm_35