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https://github.com/c64scene-ar/llvm-6502.git
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R600: Expand vector float operations for both SI and R600
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188596 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
62c7749437
commit
0991c314d7
@ -115,14 +115,14 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
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setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
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static const int types[] = {
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static const int IntTypes[] = {
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(int)MVT::v2i32,
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(int)MVT::v4i32
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};
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const size_t NumTypes = array_lengthof(types);
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const size_t NumIntTypes = array_lengthof(IntTypes);
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for (unsigned int x = 0; x < NumTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
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for (unsigned int x = 0; x < NumIntTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x];
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//Expand the following operations for the current type by default
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setOperationAction(ISD::ADD, VT, Expand);
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setOperationAction(ISD::AND, VT, Expand);
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@ -141,6 +141,20 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::VSELECT, VT, Expand);
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setOperationAction(ISD::XOR, VT, Expand);
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}
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static const int FloatTypes[] = {
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(int)MVT::v2f32,
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(int)MVT::v4f32
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};
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const size_t NumFloatTypes = array_lengthof(FloatTypes);
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for (unsigned int x = 0; x < NumFloatTypes; ++x) {
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MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x];
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setOperationAction(ISD::FADD, VT, Expand);
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setOperationAction(ISD::FDIV, VT, Expand);
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setOperationAction(ISD::FMUL, VT, Expand);
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setOperationAction(ISD::FSUB, VT, Expand);
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}
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}
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//===----------------------------------------------------------------------===//
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@ -38,15 +38,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
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computeRegisterProperties();
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setOperationAction(ISD::FADD, MVT::v4f32, Expand);
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setOperationAction(ISD::FADD, MVT::v2f32, Expand);
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setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
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setOperationAction(ISD::FMUL, MVT::v2f32, Expand);
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setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
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setOperationAction(ISD::FDIV, MVT::v2f32, Expand);
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setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
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setOperationAction(ISD::FSUB, MVT::v2f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f32, Custom);
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setOperationAction(ISD::FSIN, MVT::f32, Custom);
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@ -1,23 +1,23 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; CHECK: @fadd_f32
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fadd_f32() {
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%r0 = call float @llvm.R600.load.input(i32 0)
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%r1 = call float @llvm.R600.load.input(i32 1)
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%r2 = fadd float %r0, %r1
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call void @llvm.AMDGPU.store.output(float %r2, i32 0)
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; R600-CHECK: @fadd_f32
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
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; SI-CHECK: @fadd_f32
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; SI-CHECK: V_ADD_F32
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define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fadd float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fadd_v2f32
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; CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; R600-CHECK: @fadd_v2f32
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; R600-CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; R600-CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; SI-CHECK: @fadd_v2f32
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; SI-CHECK: V_ADD_F32
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; SI-CHECK: V_ADD_F32
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define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fadd <2 x float> %a, %b
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@ -25,12 +25,16 @@ entry:
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ret void
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}
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; CHECK: @fadd_v4f32
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: @fadd_v4f32
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-CHECK: @fadd_v4f32
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; SI-CHECK: V_ADD_F32
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; SI-CHECK: V_ADD_F32
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; SI-CHECK: V_ADD_F32
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; SI-CHECK: V_ADD_F32
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define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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@ -1,14 +1,20 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; These tests check that fdiv is expanded correctly and also test that the
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; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
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; instruction groups.
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; CHECK: @fdiv_v2f32
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; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; R600-CHECK: @fdiv_v2f32
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; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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; SI-CHECK: @fdiv_v2f32
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; SI-CHECK-DAG: V_RCP_F32
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; SI-CHECK-DAG: V_MUL_F32
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; SI-CHECK-DAG: V_RCP_F32
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; SI-CHECK-DAG: V_MUL_F32
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define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fdiv <2 x float> %a, %b
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@ -16,16 +22,24 @@ entry:
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ret void
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}
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; CHECK: @fdiv_v4f32
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; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-CHECK: @fdiv_v4f32
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; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; SI-CHECK: @fdiv_v4f32
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; SI-CHECK-DAG: V_RCP_F32
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; SI-CHECK-DAG: V_MUL_F32
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; SI-CHECK-DAG: V_RCP_F32
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; SI-CHECK-DAG: V_MUL_F32
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; SI-CHECK-DAG: V_RCP_F32
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; SI-CHECK-DAG: V_MUL_F32
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; SI-CHECK-DAG: V_RCP_F32
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; SI-CHECK-DAG: V_MUL_F32
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define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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@ -1,23 +1,27 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; CHECK: @fmul_f32
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; CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define void @fmul_f32() {
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%r0 = call float @llvm.R600.load.input(i32 0)
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%r1 = call float @llvm.R600.load.input(i32 1)
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%r2 = fmul float %r0, %r1
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call void @llvm.AMDGPU.store.output(float %r2, i32 0)
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ret void
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; R600-CHECK: @fmul_f32
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; R600-CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
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; SI-CHECK: @fmul_f32
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; SI-CHECK: V_MUL_F32
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define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fmul float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fmul_v2f32
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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; R600-CHECK: @fmul_v2f32
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; R600-CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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; R600-CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
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; SI-CHECK: @fmul_v2f32
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; SI-CHECK: V_MUL_F32
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; SI-CHECK: V_MUL_F32
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define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fmul <2 x float> %a, %b
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@ -25,12 +29,16 @@ entry:
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ret void
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}
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; CHECK: @fmul_v4f32
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: @fmul_v4f32
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; R600-CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI-CHECK: @fmul_v4f32
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; SI-CHECK: V_MUL_F32
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; SI-CHECK: V_MUL_F32
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; SI-CHECK: V_MUL_F32
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; SI-CHECK: V_MUL_F32
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define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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@ -1,23 +1,27 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; CHECK: @fsub_f32
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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define void @fsub_f32() {
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%r0 = call float @llvm.R600.load.input(i32 0)
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%r1 = call float @llvm.R600.load.input(i32 1)
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%r2 = fsub float %r0, %r1
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call void @llvm.AMDGPU.store.output(float %r2, i32 0)
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ret void
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; R600-CHECK: @fsub_f32
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
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; SI-CHECK: @fsub_f32
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; SI-CHECK: V_SUB_F32
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define void @fsub_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fsub float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; CHECK: @fsub_v2f32
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; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
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; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
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; R600-CHECK: @fsub_v2f32
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; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
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; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
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; SI-CHECK: @fsub_v2f32
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; SI-CHECK: V_SUB_F32
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; SI-CHECK: V_SUB_F32
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define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fsub <2 x float> %a, %b
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@ -25,11 +29,16 @@ entry:
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ret void
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}
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; CHECK: @fsub_v4f32
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: @fsub_v4f32
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
|
||||
; SI-CHECK: @fsub_v4f32
|
||||
; SI-CHECK: V_SUB_F32
|
||||
; SI-CHECK: V_SUB_F32
|
||||
; SI-CHECK: V_SUB_F32
|
||||
; SI-CHECK: V_SUB_F32
|
||||
define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
|
||||
%a = load <4 x float> addrspace(1) * %in
|
||||
|
||||
Loading…
Reference in New Issue
Block a user