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ARM: add test for crc32 instructions in CodeGen.

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Somehow we seem to have ended up without any actual tests of the
CodeGen side. Easy enough to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2015-01-14 01:43:33 +00:00
parent a8f0d2f673
commit 09bec94c16
1 changed files with 58 additions and 0 deletions
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58
test/CodeGen/ARM/crc32.ll Normal file
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; RUN: llc -mtriple=thumbv8 -o - %s | FileCheck %s
define i32 @test_crc32b(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32b:
; CHECK: crc32b r0, r0, r1
%bits = zext i8 %next to i32
%val = call i32 @llvm.arm.crc32b(i32 %cur, i32 %bits)
ret i32 %val
}
define i32 @test_crc32h(i32 %cur, i16 %next) {
; CHECK-LABEL: test_crc32h:
; CHECK: crc32h r0, r0, r1
%bits = zext i16 %next to i32
%val = call i32 @llvm.arm.crc32h(i32 %cur, i32 %bits)
ret i32 %val
}
define i32 @test_crc32w(i32 %cur, i32 %next) {
; CHECK-LABEL: test_crc32w:
; CHECK: crc32w r0, r0, r1
%val = call i32 @llvm.arm.crc32w(i32 %cur, i32 %next)
ret i32 %val
}
define i32 @test_crc32cb(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32cb:
; CHECK: crc32cb r0, r0, r1
%bits = zext i8 %next to i32
%val = call i32 @llvm.arm.crc32cb(i32 %cur, i32 %bits)
ret i32 %val
}
define i32 @test_crc32ch(i32 %cur, i16 %next) {
; CHECK-LABEL: test_crc32ch:
; CHECK: crc32ch r0, r0, r1
%bits = zext i16 %next to i32
%val = call i32 @llvm.arm.crc32ch(i32 %cur, i32 %bits)
ret i32 %val
}
define i32 @test_crc32cw(i32 %cur, i32 %next) {
; CHECK-LABEL: test_crc32cw:
; CHECK: crc32cw r0, r0, r1
%val = call i32 @llvm.arm.crc32cw(i32 %cur, i32 %next)
ret i32 %val
}
declare i32 @llvm.arm.crc32b(i32, i32)
declare i32 @llvm.arm.crc32h(i32, i32)
declare i32 @llvm.arm.crc32w(i32, i32)
declare i32 @llvm.arm.crc32x(i32, i64)
declare i32 @llvm.arm.crc32cb(i32, i32)
declare i32 @llvm.arm.crc32ch(i32, i32)
declare i32 @llvm.arm.crc32cw(i32, i32)
declare i32 @llvm.arm.crc32cx(i32, i64)