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Completely eliminate def&use operands. Now a register operand is EITHER a

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def operand or a use operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-09-05 02:31:13 +00:00
parent 2926869b4a
commit 09e460662a
10 changed files with 78 additions and 106 deletions
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16
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -255,11 +255,11 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
// the machine instruction.
unsigned ResultReg =
RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
MI->addRegOperand(ResultReg, MachineOperand::Def);
MI->addRegOperand(ResultReg, true);
for (unsigned i = 1; i != NumResults; ++i) {
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
}
return ResultReg;
}
@ -291,7 +291,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
MI->addRegOperand(VReg, MachineOperand::Use);
MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@ -307,7 +307,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
MI->addRegOperand(R->getReg(), MachineOperand::Use);
MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
@ -349,7 +349,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
MI->addRegOperand(VReg, MachineOperand::Use);
MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@ -402,7 +402,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
MI->addRegOperand(Reg, MachineOperand::Def);
MI->addRegOperand(Reg, true);
break;
}
}
@ -529,13 +529,13 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addRegOperand(Reg, MachineOperand::Use);
MI->addRegOperand(Reg, false);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
MI->addRegOperand(Reg, MachineOperand::Def);
MI->addRegOperand(Reg, true);
}
break;
case 3: { // Immediate.