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https://github.com/c64scene-ar/llvm-6502.git
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Fix FMDRR encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59088 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
cb5201f3b2
commit
0a0ab1387a
@ -342,6 +342,7 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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break;
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case ARMII::VFPConv1Frm:
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case ARMII::VFPConv2Frm:
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case ARMII::VFPConv3Frm:
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emitVFPConversionInstruction(MI);
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break;
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case ARMII::VFPLdStFrm:
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@ -1080,27 +1081,41 @@ void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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unsigned OpIdx = 0;
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// FMDRR encodes registers in reverse order.
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unsigned Form = TID.TSFlags & ARMII::FormMask;
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unsigned OpIdx = (Form == ARMII::VFPConv2Frm) ? 2 : 0;
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// Encode Dd / Sd.
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unsigned RegD = getMachineOpValue(MI, OpIdx++);
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unsigned RegD = getMachineOpValue(MI, OpIdx);
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Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
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Binary |= (RegD & 0x10) << ARMII::D_BitShift;
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if (Form == ARMII::VFPConv2Frm)
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--OpIdx;
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else
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++OpIdx;
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// Encode Dn / Sn.
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if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) {
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unsigned RegN = getMachineOpValue(MI, OpIdx++);
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if (Form == ARMII::VFPConv1Frm || Form == ARMII::VFPConv2Frm) {
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unsigned RegN = getMachineOpValue(MI, OpIdx);
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Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
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Binary |= (RegN & 0x10) << ARMII::N_BitShift;
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if (Form == ARMII::VFPConv2Frm)
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--OpIdx;
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else
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++OpIdx;
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// FMRS / FMSR do not have Rm.
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if (!TID.OpInfo[2].isPredicate()) {
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unsigned RegM = getMachineOpValue(MI, OpIdx++);
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if (TID.getNumOperands() > OpIdx && MI.getOperand(OpIdx).isReg()) {
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unsigned RegM = getMachineOpValue(MI, OpIdx);
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Binary |= (RegM & 0x0f);
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Binary |= (RegM & 0x10) << ARMII::M_BitShift;
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} else if (Form == ARMII::VFPConv2Frm) {
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// FMDRR encodes definition register in Dm field.
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Binary |= getMachineOpValue(MI, 0);
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}
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} else {
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unsigned RegM = getMachineOpValue(MI, OpIdx++);
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assert(Form == ARMII::VFPConv3Frm && "Unsupported format!");
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unsigned RegM = getMachineOpValue(MI, OpIdx);
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Binary |= (RegM & 0x0f);
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Binary |= (RegM & 0x10) << ARMII::M_BitShift;
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}
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@ -41,11 +41,12 @@ def VFPUnaryFrm : Format<15>;
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def VFPBinaryFrm : Format<16>;
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def VFPConv1Frm : Format<17>;
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def VFPConv2Frm : Format<18>;
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def VFPLdStFrm : Format<19>;
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def VFPLdStMulFrm : Format<20>;
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def VFPMiscFrm : Format<21>;
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def VFPConv3Frm : Format<19>;
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def VFPLdStFrm : Format<20>;
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def VFPLdStMulFrm : Format<21>;
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def VFPMiscFrm : Format<22>;
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def ThumbFrm : Format<22>;
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def ThumbFrm : Format<23>;
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// Misc flag for data processing instructions that indicates whether
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// the instruction has a Rn register operand.
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@ -827,9 +828,17 @@ class AVConv1I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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let Inst{4} = 1;
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}
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class AVConv2I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
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class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
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string asm, list<dag> pattern>
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: AI<oops, iops, VFPConv2Frm, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{11-8} = opcod2;
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let Inst{4} = 1;
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}
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class AVConv3I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
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dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
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: AI<oops, iops, VFPConv3Frm, opc, asm, pattern> {
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let Inst{27-20} = opcod1;
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let Inst{19-16} = opcod2;
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let Inst{11-8} = opcod3;
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@ -105,12 +105,13 @@ namespace ARMII {
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VFPBinaryFrm = 16 << FormShift,
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VFPConv1Frm = 17 << FormShift,
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VFPConv2Frm = 18 << FormShift,
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VFPLdStFrm = 19 << FormShift,
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VFPLdStMulFrm = 20 << FormShift,
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VFPMiscFrm = 21 << FormShift,
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VFPConv3Frm = 19 << FormShift,
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VFPLdStFrm = 20 << FormShift,
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VFPLdStMulFrm = 21 << FormShift,
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VFPMiscFrm = 22 << FormShift,
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// Thumb format
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ThumbFrm = 22 << FormShift,
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ThumbFrm = 23 << FormShift,
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//===------------------------------------------------------------------===//
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// Field shifts - such shifts are used to set field while generating
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@ -235,7 +235,7 @@ def FMRRD : AVConv1I<0b11000101, 0b1011,
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// FMDHR: GPR -> SPR
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// FMDLR: GPR -> SPR
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def FMDRR : AVConv1I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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def FMDRR : AVConv2I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
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"fmdrr", " $dst, $src1, $src2",
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[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
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@ -251,25 +251,25 @@ def FMDRR : AVConv1I<0b11000100, 0b1011, (outs DPR:$dst), (ins GPR:$src1, GPR:$s
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// Int to FP:
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def FSITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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def FSITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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"fsitod", " $dst, $a",
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[(set DPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FSITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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def FSITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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"fsitos", " $dst, $a",
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[(set SPR:$dst, (arm_sitof SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FUITOD : AVConv2I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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def FUITOD : AVConv3I<0b11101011, 0b1000, 0b1011, (outs DPR:$dst), (ins SPR:$a),
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"fuitod", " $dst, $a",
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[(set DPR:$dst, (arm_uitof SPR:$a))]> {
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let Inst{7} = 0; // Z bit
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}
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def FUITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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def FUITOS : AVConv3I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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"fuitos", " $dst, $a",
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[(set SPR:$dst, (arm_uitof SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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@ -278,28 +278,28 @@ def FUITOS : AVConv2I<0b11101011, 0b1000, 0b1010, (outs SPR:$dst), (ins SPR:$a),
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// FP to Int:
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// Always set Z bit in the instruction, i.e. "round towards zero" variants.
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def FTOSIZD : AVConv2I<0b11101011, 0b1101, 0b1011,
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def FTOSIZD : AVConv3I<0b11101011, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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"ftosizd", " $dst, $a",
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[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOSIZS : AVConv2I<0b11101011, 0b1101, 0b1010,
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def FTOSIZS : AVConv3I<0b11101011, 0b1101, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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"ftosizs", " $dst, $a",
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[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOUIZD : AVConv2I<0b11101011, 0b1100, 0b1011,
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def FTOUIZD : AVConv3I<0b11101011, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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"ftouizd", " $dst, $a",
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[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
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let Inst{7} = 1; // Z bit
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}
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def FTOUIZS : AVConv2I<0b11101011, 0b1100, 0b1010,
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def FTOUIZS : AVConv3I<0b11101011, 0b1100, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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"ftouizs", " $dst, $a",
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[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
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