mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-26 12:20:42 +00:00
Properly handle divides. As a bonus - implement memory versions of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
@@ -30,6 +30,10 @@
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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static const unsigned subreg_32bit = 1;
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static const unsigned subreg_even = 1;
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static const unsigned subreg_odd = 2;
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namespace {
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/// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
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/// instead of register numbers for the leaves of the matched tree.
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@@ -129,6 +133,10 @@ namespace {
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SDValue &Base, SDValue &Disp, SDValue &Index);
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SDNode *Select(SDValue Op);
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bool TryFoldLoad(SDValue P, SDValue N,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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bool is12Bit, unsigned Depth = 0);
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bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
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@@ -573,6 +581,15 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
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return false;
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}
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bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
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SDValue &Base, SDValue &Disp, SDValue &Index) {
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if (ISD::isNON_EXTLoad(N.getNode()) &&
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N.hasOneUse() &&
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IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
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return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
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return false;
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void SystemZDAGToDAGISel::InstructionSelect() {
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@@ -593,7 +610,9 @@ void SystemZDAGToDAGISel::InstructionSelect() {
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SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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SDNode *Node = Op.getNode();
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MVT NVT = Node->getValueType(0);
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DebugLoc dl = Op.getDebugLoc();
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unsigned Opcode = Node->getOpcode();
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// Dump information about the Node being selected
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#ifndef NDEBUG
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@@ -611,8 +630,195 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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DOUT << "\n";
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Indent -= 2;
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#endif
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return NULL; // Already selected.
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}
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switch (Opcode) {
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default: break;
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case ISD::SDIVREM: {
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unsigned Opc, MOpc, ClrOpc = 0;
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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MVT ResVT;
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switch (NVT.getSimpleVT()) {
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default: assert(0 && "Unsupported VT!");
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case MVT::i32:
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Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
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ClrOpc = SystemZ::MOV32ri16;
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ResVT = MVT::v2i32;
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break;
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case MVT::i64:
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Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
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ResVT = MVT::v2i64;
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break;
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}
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SDValue Tmp0, Tmp1, Tmp2;
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bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
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// Prepare the dividend
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SDNode *Dividend = N0.getNode();
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// Insert prepared dividend into suitable 'subreg'
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SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
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dl, ResVT);
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Dividend =
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CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
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SDValue(Tmp, 0), SDValue(Dividend, 0),
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CurDAG->getTargetConstant(subreg_odd, MVT::i32));
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// Zero out even subreg, if needed
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if (ClrOpc) {
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SDNode * ZeroHi = CurDAG->getTargetNode(SystemZ::MOV32ri16, dl, NVT,
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CurDAG->getTargetConstant(0, MVT::i32));
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Dividend =
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CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
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SDValue(Dividend, 0),
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SDValue(ZeroHi, 0),
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CurDAG->getTargetConstant(subreg_even, MVT::i32));
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}
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SDNode *Result;
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SDValue DivVal = SDValue(Dividend, 0);
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if (foldedLoad) {
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SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
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Result = CurDAG->getTargetNode(MOpc, dl, ResVT, Ops, array_lengthof(Ops));
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// Update the chain.
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ReplaceUses(N1.getValue(1), SDValue(Result, 0));
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} else {
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Result = CurDAG->getTargetNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
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}
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// Copy the division (odd subreg) result, if it is needed.
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if (!Op.getValue(0).use_empty()) {
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SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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SDValue(Result, 0),
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CurDAG->getTargetConstant(subreg_odd,
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MVT::i32));
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ReplaceUses(Op.getValue(0), SDValue(Div, 0));
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(Result->dump(CurDAG));
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DOUT << "\n";
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#endif
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}
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// Copy the remainder (even subreg) result, if it is needed.
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if (!Op.getValue(1).use_empty()) {
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SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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SDValue(Result, 0),
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CurDAG->getTargetConstant(subreg_even,
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MVT::i32));
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ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(Result->dump(CurDAG));
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DOUT << "\n";
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#endif
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}
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#ifndef NDEBUG
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Indent -= 2;
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#endif
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return NULL;
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}
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case ISD::UDIVREM: {
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unsigned Opc, MOpc, ClrOpc;
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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MVT ResVT;
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switch (NVT.getSimpleVT()) {
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default: assert(0 && "Unsupported VT!");
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case MVT::i32:
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Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
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ClrOpc = SystemZ::MOV32ri16;
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ResVT = MVT::v2i32;
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break;
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case MVT::i64:
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Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
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ClrOpc = SystemZ::MOV64ri16;
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ResVT = MVT::v2i64;
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break;
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}
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SDValue Tmp0, Tmp1, Tmp2;
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bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
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// Prepare the dividend
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SDNode *Dividend = N0.getNode();
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// Insert prepared dividend into suitable 'subreg'
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SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
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dl, ResVT);
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Dividend =
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CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
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SDValue(Tmp, 0), SDValue(Dividend, 0),
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CurDAG->getTargetConstant(subreg_odd, MVT::i32));
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// Zero out even subreg, if needed
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SDNode * ZeroHi = CurDAG->getTargetNode(ClrOpc, dl, NVT,
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CurDAG->getTargetConstant(0,
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MVT::i32));
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Dividend =
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CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
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SDValue(Dividend, 0),
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SDValue(ZeroHi, 0),
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CurDAG->getTargetConstant(subreg_even, MVT::i32));
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SDValue DivVal = SDValue(Dividend, 0);
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SDNode *Result;
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if (foldedLoad) {
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SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
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Result = CurDAG->getTargetNode(MOpc, dl,ResVT,
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Ops, array_lengthof(Ops));
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// Update the chain.
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ReplaceUses(N1.getValue(1), SDValue(Result, 0));
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} else {
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Result = CurDAG->getTargetNode(Opc, dl, ResVT, DivVal, N1);
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}
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// Copy the division (odd subreg) result, if it is needed.
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if (!Op.getValue(0).use_empty()) {
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SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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SDValue(Result, 0),
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CurDAG->getTargetConstant(subreg_odd,
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MVT::i32));
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ReplaceUses(Op.getValue(0), SDValue(Div, 0));
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(Result->dump(CurDAG));
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DOUT << "\n";
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#endif
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}
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// Copy the remainder (even subreg) result, if it is needed.
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if (!Op.getValue(1).use_empty()) {
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SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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SDValue(Result, 0),
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CurDAG->getTargetConstant(subreg_even,
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MVT::i32));
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ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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DEBUG(Result->dump(CurDAG));
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DOUT << "\n";
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#endif
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}
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#ifndef NDEBUG
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Indent -= 2;
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#endif
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return NULL;
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(Op);
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@@ -43,7 +43,9 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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// Set up the register classes.
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addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
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addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
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addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
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addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
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addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
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// Compute derived properties from the register classes
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computeRegisterProperties();
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@@ -70,6 +72,15 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::SDIV, MVT::i64, Expand);
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setOperationAction(ISD::UDIV, MVT::i64, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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// FIXME: Can we lower these 2 efficiently?
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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@@ -580,22 +580,34 @@ def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
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"msgfr\t{$dst, $src2}",
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[(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
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def SDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
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"dr\t{$dst, $src2}",
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[]>;
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def SDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
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"dr\t{$dst, $src2}",
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[]>;
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def SDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
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"dsgr\t{$dst, $src2}",
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[]>;
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def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
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"dsgr\t{$dst, $src2}",
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[]>;
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def UDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
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"dlr\t{$dst, $src2}",
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[]>;
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def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
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"dlgr\t{$dst, $src2}",
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[]>;
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def UDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
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"dlr\t{$dst, $src2}",
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[]>;
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def UDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
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"dlgr\t{$dst, $src2}",
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[]>;
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let mayLoad = 1 in {
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def SDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
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"d\t{$dst, $src2}",
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[]>;
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def SDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
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"dsg\t{$dst, $src2}",
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[]>;
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def UDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
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"dl\t{$dst, $src2}",
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[]>;
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def UDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
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"dlg\t{$dst, $src2}",
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[]>;
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} // mayLoad
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} // isTwoAddress = 1
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//===----------------------------------------------------------------------===//
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@@ -790,51 +802,5 @@ def : Pat<(mulhu GR64:$src1, GR64:$src2),
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GR64:$src2),
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subreg_even)>;
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// divs
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// FIXME: Add memory versions
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def : Pat<(sdiv GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd),
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GR32:$src2),
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subreg_odd)>;
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def : Pat<(sdiv GR64:$src1, GR64:$src2),
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(EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_odd)>;
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def : Pat<(udiv GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd),
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GR32:$src2),
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subreg_odd)>;
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def : Pat<(udiv GR64:$src1, GR64:$src2),
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(EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_odd)>;
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// rems
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// FIXME: Add memory versions
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def : Pat<(srem GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd),
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GR32:$src2),
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subreg_even)>;
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def : Pat<(srem GR64:$src1, GR64:$src2),
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(EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_even)>;
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def : Pat<(urem GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd),
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GR32:$src2),
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subreg_even)>;
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def : Pat<(urem GR64:$src1, GR64:$src2),
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(EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_even)>;
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def : Pat<(i32 imm:$src),
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(EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
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@@ -332,7 +332,7 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
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}
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// Even-odd register pairs
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def GR64P : RegisterClass<"SystemZ", [i64], 64,
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def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
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[R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]>
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{
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let SubRegClassList = [GR32, GR32];
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@@ -368,7 +368,7 @@ def GR64P : RegisterClass<"SystemZ", [i64], 64,
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}];
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}
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def GR128 : RegisterClass<"SystemZ", [i128], 128,
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def GR128 : RegisterClass<"SystemZ", [i128, v2i64], 128,
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[R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
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{
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let SubRegClassList = [GR64, GR64];
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@@ -1,7 +1,7 @@
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; RUN: llvm-as < %s | llc | grep dsgr | count 2
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; RUN: llvm-as < %s | llc | grep dr | count 2
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||||
; RUN: llvm-as < %s | llc | grep dlr | count 2
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||||
; RUN: llvm-as < %s | llc | grep dlgr | count 2
|
||||
; RUN: llvm-as < %s | llc | grep dsgr | count 2
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; RUN: llvm-as < %s | llc | grep dr | count 2
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; RUN: llvm-as < %s | llc | grep dlr | count 2
|
||||
; RUN: llvm-as < %s | llc | grep dlgr | count 2
|
||||
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
|
||||
target triple = "s390x-unknown-linux-gnu"
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
; RUN: llvm-as < %s | llc | grep {d.%} | count 2
|
||||
; RUN: llvm-as < %s | llc | grep dsg | count 2
|
||||
; RUN: llvm-as < %s | llc | grep {dl.%} | count 2
|
||||
; RUN: llvm-as < %s | llc | grep dlg | count 2
|
||||
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
|
||||
target triple = "s390x-unknown-linux-gnu"
|
||||
|
||||
define i64 @div(i64 %a, i64* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i64* %b
|
||||
%div = sdiv i64 %a, %b1
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i64 @div1(i64 %a, i64* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i64* %b
|
||||
%div = udiv i64 %a, %b1
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i64 @rem(i64 %a, i64* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i64* %b
|
||||
%div = srem i64 %a, %b1
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i64 @rem1(i64 %a, i64* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i64* %b
|
||||
%div = urem i64 %a, %b1
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i32 @div2(i32 %a, i32* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i32* %b
|
||||
%div = sdiv i32 %a, %b1
|
||||
ret i32 %div
|
||||
}
|
||||
|
||||
define i32 @div3(i32 %a, i32* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i32* %b
|
||||
%div = udiv i32 %a, %b1
|
||||
ret i32 %div
|
||||
}
|
||||
|
||||
define i32 @rem2(i32 %a, i32* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i32* %b
|
||||
%div = srem i32 %a, %b1
|
||||
ret i32 %div
|
||||
}
|
||||
|
||||
define i32 @rem3(i32 %a, i32* %b) nounwind readnone {
|
||||
entry:
|
||||
%b1 = load i32* %b
|
||||
%div = urem i32 %a, %b1
|
||||
ret i32 %div
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user