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[mips] Refactor load/store left/right and load-link and store-conditional
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -142,28 +142,25 @@ defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>;
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defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>;
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defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>;
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defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>;
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defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
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defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
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defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
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defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
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}
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defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>;
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defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>;
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defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>;
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defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>;
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defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
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defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
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defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
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defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
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/// Load-linked, Store-conditional
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def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let isCodeGenOnly = 1;
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let Predicates = [NotN64, HasStdEnc] in {
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def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>;
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def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>;
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}
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def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let isCodeGenOnly = 1;
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let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
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def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>;
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def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>;
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}
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/// Jump and Branch Instructions
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@ -435,58 +435,36 @@ multiclass StoreM<string opstr, PatFrag OpNode, RegisterClass RC> {
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// Load/Store Left/Right
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let canFoldAsLoad = 1 in
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class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
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RegisterClass RC, Operand MemOpnd> :
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FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
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!strconcat(instr_asm, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
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class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
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Operand MemOpnd> :
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InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMem";
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string Constraints = "$src = $rt";
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}
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class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
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RegisterClass RC, Operand MemOpnd>:
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FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
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!strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
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IIStore>;
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class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
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Operand MemOpnd>:
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InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMem";
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}
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// 32-bit load left/right.
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multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
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def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
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multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
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def #NAME# : LoadLeftRight<opstr, OpNode, RC, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
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def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let isCodeGenOnly = 1;
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}
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}
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// 64-bit load left/right.
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multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
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def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
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multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
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def #NAME# : StoreLeftRight<opstr, OpNode, RC, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let isCodeGenOnly = 1;
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}
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}
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// 32-bit store left/right.
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multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
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def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let isCodeGenOnly = 1;
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}
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}
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// 64-bit store left/right.
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multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
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def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
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def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let isCodeGenOnly = 1;
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@ -736,15 +714,17 @@ multiclass AtomicCmpSwap32<PatFrag Op> {
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}
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}
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class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
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FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
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!strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
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class LLBase<string opstr, RegisterClass RC, Operand Mem> :
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InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMem";
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let mayLoad = 1;
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}
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class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
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FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
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!strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
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class SCBase<string opstr, RegisterClass RC, Operand Mem> :
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InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
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let DecoderMethod = "DecodeMem";
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let mayStore = 1;
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let Constraints = "$rt = $dst";
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}
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@ -850,10 +830,10 @@ defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>;
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defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>;
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/// load/store left/right
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defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
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defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
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defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
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defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
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defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
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defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
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defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
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defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
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let hasSideEffects = 1 in
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def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
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@ -867,18 +847,14 @@ def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
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}
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/// Load-linked, Store-conditional
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def LL : LLBase<0x30, "ll", CPURegs, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let Predicates = [NotN64, HasStdEnc] in {
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def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>;
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def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>;
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}
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def SC : SCBase<0x38, "sc", CPURegs, mem>,
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Requires<[NotN64, HasStdEnc]>;
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def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
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Requires<[IsN64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
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def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>;
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def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>;
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}
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/// Jump and Branch Instructions
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