mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Updated ModuloScheduling. It makes it all the wya through register allocation on the new code!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15351 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -49,12 +49,12 @@ bool MSSchedule::insert(MSchedGraphNode *node, int cycle) {
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bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) {
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//Get Resource usage for this instruction
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const TargetSchedInfo & msi = node->getParent()->getTarget()->getSchedInfo();
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const TargetSchedInfo *msi = node->getParent()->getTarget()->getSchedInfo();
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int currentCycle = cycle;
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bool success = true;
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//Get resource usage for this instruction
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InstrRUsage rUsage = msi.getInstrRUsage(node->getInst()->getOpcode());
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InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
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std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
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//Loop over resources in each cycle and increments their usage count
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@ -101,7 +101,7 @@ bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) {
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int oldCycle = cycle;
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DEBUG(std::cerr << "Backtrack\n");
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//Get resource usage for this instruction
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InstrRUsage rUsage = msi.getInstrRUsage(node->getInst()->getOpcode());
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InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
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std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
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//Loop over resources in each cycle and increments their usage count
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@ -103,7 +103,7 @@ MSchedGraph::~MSchedGraph () {
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void MSchedGraph::buildNodesAndEdges() {
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//Get Machine target information for calculating latency
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const TargetInstrInfo &MTI = Target.getInstrInfo();
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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std::vector<MSchedGraphNode*> memInstructions;
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std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
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@ -124,16 +124,16 @@ void MSchedGraph::buildNodesAndEdges() {
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#if 0 // FIXME: LOOK INTO THIS
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//Check if subsequent instructions can be issued before
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//the result is ready, if so use min delay.
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if(MTI.hasResultInterlock(MIopCode))
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delay = MTI.minLatency(MIopCode);
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if(MTI->hasResultInterlock(MIopCode))
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delay = MTI->minLatency(MIopCode);
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else
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#endif
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//Get delay
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delay = MTI.maxLatency(opCode);
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delay = MTI->maxLatency(opCode);
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//Create new node for this machine instruction and add to the graph.
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//Create only if not a nop
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if(MTI.isNop(opCode))
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if(MTI->isNop(opCode))
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continue;
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//Add PHI to phi instruction list to be processed later
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@ -143,7 +143,7 @@ void MSchedGraph::buildNodesAndEdges() {
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bool isBranch = false;
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//We want to flag the branch node to treat it special
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if(MTI.isBranch(opCode))
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if(MTI->isBranch(opCode))
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isBranch = true;
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//Node is created and added to the graph automatically
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@ -152,7 +152,7 @@ void MSchedGraph::buildNodesAndEdges() {
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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//Check OpCode to keep track of memory operations to add memory dependencies later.
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if(MTI.isLoad(opCode) || MTI.isStore(opCode))
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if(MTI->isLoad(opCode) || MTI->isStore(opCode))
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memInstructions.push_back(node);
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//Loop over all operands, and put them into the register number to
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@ -370,7 +370,7 @@ void MSchedGraph::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >&
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void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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//Get Target machine instruction info
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const TargetInstrInfo& TMI = Target.getInstrInfo();
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const TargetInstrInfo *TMI = Target.getInstrInfo();
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//Loop over all memory instructions in the vector
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//Knowing that they are in execution, add true, anti, and output dependencies
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@ -383,15 +383,15 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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for(unsigned destIndex = srcIndex + 1; destIndex < memInst.size(); ++destIndex) {
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI.isLoad(srcNodeOpCode))
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isLoad(srcNodeOpCode))
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep);
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//If source is a store, add output and true dependencies
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if(TMI.isStore(srcNodeOpCode)) {
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isStore(srcNodeOpCode)) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::OutputDep);
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@ -405,13 +405,13 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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//All instructions before the src in execution order have an iteration delay of 1
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for(unsigned destIndex = 0; destIndex < srcIndex; ++destIndex) {
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI.isLoad(srcNodeOpCode))
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isLoad(srcNodeOpCode))
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep, 1);
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if(TMI.isStore(srcNodeOpCode)) {
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isStore(srcNodeOpCode)) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::OutputDep, 1);
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File diff suppressed because it is too large
Load Diff
@ -89,13 +89,18 @@ namespace llvm {
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void predIntersect(std::vector<MSchedGraphNode*> &CurrentSet, std::vector<MSchedGraphNode*> &IntersectResult);
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void succIntersect(std::vector<MSchedGraphNode*> &CurrentSet, std::vector<MSchedGraphNode*> &IntersectResult);
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void reconstructLoop(const MachineBasicBlock*);
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void reconstructLoop(MachineBasicBlock*);
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//void saveValue(const MachineInstr*, const std::set<Value*>&, std::vector<Value*>*);
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void writePrologues(std::vector<MachineBasicBlock *> &prologues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_prologues);
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void writePrologues(std::vector<MachineBasicBlock *> &prologues, MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_prologues, std::map<const Value*, std::pair<const MSchedGraphNode*, int> > &valuesToSave, std::map<Value*, std::map<int, std::vector<Value*> > > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
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void writeEpilogues(std::vector<MachineBasicBlock *> &epilogues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_epilogues);
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void writeEpilogues(std::vector<MachineBasicBlock *> &epilogues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_epilogues, std::map<const Value*, std::pair<const MSchedGraphNode*, int> > &valuesToSave,std::map<Value*, std::map<int, std::vector<Value*> > > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
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void writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map<const Value*, std::pair<const MSchedGraphNode*, int> > &valuesToSave, std::map<Value*, std::map<int, std::vector<Value*> > > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
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void removePHIs(const MachineBasicBlock *origBB, std::vector<MachineBasicBlock *> &prologues, std::vector<MachineBasicBlock *> &epilogues, MachineBasicBlock *kernelBB, std::map<Value*, MachineBasicBlock*> &newValLocation);
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public:
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ModuloSchedulingPass(TargetMachine &targ) : target(targ) {}
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@ -49,12 +49,12 @@ bool MSSchedule::insert(MSchedGraphNode *node, int cycle) {
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bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) {
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//Get Resource usage for this instruction
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const TargetSchedInfo & msi = node->getParent()->getTarget()->getSchedInfo();
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const TargetSchedInfo *msi = node->getParent()->getTarget()->getSchedInfo();
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int currentCycle = cycle;
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bool success = true;
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//Get resource usage for this instruction
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InstrRUsage rUsage = msi.getInstrRUsage(node->getInst()->getOpcode());
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InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
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std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
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//Loop over resources in each cycle and increments their usage count
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@ -101,7 +101,7 @@ bool MSSchedule::resourcesFree(MSchedGraphNode *node, int cycle) {
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int oldCycle = cycle;
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DEBUG(std::cerr << "Backtrack\n");
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//Get resource usage for this instruction
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InstrRUsage rUsage = msi.getInstrRUsage(node->getInst()->getOpcode());
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InstrRUsage rUsage = msi->getInstrRUsage(node->getInst()->getOpcode());
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std::vector<std::vector<resourceId_t> > resources = rUsage.resourcesByCycle;
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//Loop over resources in each cycle and increments their usage count
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@ -103,7 +103,7 @@ MSchedGraph::~MSchedGraph () {
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void MSchedGraph::buildNodesAndEdges() {
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//Get Machine target information for calculating latency
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const TargetInstrInfo &MTI = Target.getInstrInfo();
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const TargetInstrInfo *MTI = Target.getInstrInfo();
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std::vector<MSchedGraphNode*> memInstructions;
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std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
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@ -124,16 +124,16 @@ void MSchedGraph::buildNodesAndEdges() {
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#if 0 // FIXME: LOOK INTO THIS
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//Check if subsequent instructions can be issued before
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//the result is ready, if so use min delay.
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if(MTI.hasResultInterlock(MIopCode))
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delay = MTI.minLatency(MIopCode);
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if(MTI->hasResultInterlock(MIopCode))
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delay = MTI->minLatency(MIopCode);
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else
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#endif
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//Get delay
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delay = MTI.maxLatency(opCode);
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delay = MTI->maxLatency(opCode);
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//Create new node for this machine instruction and add to the graph.
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//Create only if not a nop
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if(MTI.isNop(opCode))
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if(MTI->isNop(opCode))
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continue;
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//Add PHI to phi instruction list to be processed later
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@ -143,7 +143,7 @@ void MSchedGraph::buildNodesAndEdges() {
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bool isBranch = false;
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//We want to flag the branch node to treat it special
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if(MTI.isBranch(opCode))
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if(MTI->isBranch(opCode))
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isBranch = true;
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//Node is created and added to the graph automatically
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@ -152,7 +152,7 @@ void MSchedGraph::buildNodesAndEdges() {
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DEBUG(std::cerr << "Created Node: " << *node << "\n");
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//Check OpCode to keep track of memory operations to add memory dependencies later.
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if(MTI.isLoad(opCode) || MTI.isStore(opCode))
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if(MTI->isLoad(opCode) || MTI->isStore(opCode))
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memInstructions.push_back(node);
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//Loop over all operands, and put them into the register number to
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@ -370,7 +370,7 @@ void MSchedGraph::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >&
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void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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//Get Target machine instruction info
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const TargetInstrInfo& TMI = Target.getInstrInfo();
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const TargetInstrInfo *TMI = Target.getInstrInfo();
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//Loop over all memory instructions in the vector
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//Knowing that they are in execution, add true, anti, and output dependencies
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@ -383,15 +383,15 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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for(unsigned destIndex = srcIndex + 1; destIndex < memInst.size(); ++destIndex) {
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI.isLoad(srcNodeOpCode))
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isLoad(srcNodeOpCode))
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep);
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//If source is a store, add output and true dependencies
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if(TMI.isStore(srcNodeOpCode)) {
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isStore(srcNodeOpCode)) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::OutputDep);
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@ -405,13 +405,13 @@ void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst) {
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//All instructions before the src in execution order have an iteration delay of 1
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for(unsigned destIndex = 0; destIndex < srcIndex; ++destIndex) {
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//source is a Load, so add anti-dependencies (store after load)
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if(TMI.isLoad(srcNodeOpCode))
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isLoad(srcNodeOpCode))
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::AntiDep, 1);
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if(TMI.isStore(srcNodeOpCode)) {
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if(TMI.isStore(memInst[destIndex]->getInst()->getOpcode()))
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if(TMI->isStore(srcNodeOpCode)) {
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if(TMI->isStore(memInst[destIndex]->getInst()->getOpcode()))
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memInst[srcIndex]->addOutEdge(memInst[destIndex],
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MSchedGraphEdge::MemoryDep,
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MSchedGraphEdge::OutputDep, 1);
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File diff suppressed because it is too large
Load Diff
@ -89,13 +89,18 @@ namespace llvm {
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void predIntersect(std::vector<MSchedGraphNode*> &CurrentSet, std::vector<MSchedGraphNode*> &IntersectResult);
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void succIntersect(std::vector<MSchedGraphNode*> &CurrentSet, std::vector<MSchedGraphNode*> &IntersectResult);
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void reconstructLoop(const MachineBasicBlock*);
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void reconstructLoop(MachineBasicBlock*);
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//void saveValue(const MachineInstr*, const std::set<Value*>&, std::vector<Value*>*);
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void writePrologues(std::vector<MachineBasicBlock *> &prologues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_prologues);
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void writePrologues(std::vector<MachineBasicBlock *> &prologues, MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_prologues, std::map<const Value*, std::pair<const MSchedGraphNode*, int> > &valuesToSave, std::map<Value*, std::map<int, std::vector<Value*> > > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
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void writeEpilogues(std::vector<MachineBasicBlock *> &epilogues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_epilogues);
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void writeEpilogues(std::vector<MachineBasicBlock *> &epilogues, const MachineBasicBlock *origBB, std::vector<BasicBlock*> &llvm_epilogues, std::map<const Value*, std::pair<const MSchedGraphNode*, int> > &valuesToSave,std::map<Value*, std::map<int, std::vector<Value*> > > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
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void writeKernel(BasicBlock *llvmBB, MachineBasicBlock *machineBB, std::map<const Value*, std::pair<const MSchedGraphNode*, int> > &valuesToSave, std::map<Value*, std::map<int, std::vector<Value*> > > &newValues, std::map<Value*, MachineBasicBlock*> &newValLocation);
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void removePHIs(const MachineBasicBlock *origBB, std::vector<MachineBasicBlock *> &prologues, std::vector<MachineBasicBlock *> &epilogues, MachineBasicBlock *kernelBB, std::map<Value*, MachineBasicBlock*> &newValLocation);
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public:
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ModuloSchedulingPass(TargetMachine &targ) : target(targ) {}
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