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Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-04-15 21:00:26 +00:00
parent b485de5d8c
commit 0bf3dfbef6
32 changed files with 299 additions and 270 deletions
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4
lib/Target/Mips/Makefile
View File

@ -1,11 +1,11 @@
##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
##===- lib/Target/Mips/Makefile ---------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
##===---------------------------------------------------------------------===##
LEVEL = ../../..
LIBRARYNAME = LLVMMipsCodeGen

6
lib/Target/Mips/Mips.h
View File

@ -1,16 +1,16 @@
//===-- Mips.h - Top-level interface for Mips representation ----*- C++ -*-===//
//===-- Mips.h - Top-level interface for Mips representation ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in
// the LLVM Mips back-end.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef TARGET_MIPS_H
#define TARGET_MIPS_H

31
lib/Target/Mips/Mips.td
View File

@ -1,23 +1,23 @@
//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
//===- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// This is the top level entry point for the Mips target.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Target-independent interfaces
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
include "MipsRegisterInfo.td"
include "MipsSchedule.td"
@ -26,16 +26,17 @@ include "MipsCallingConv.td"
def MipsInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// Mips Subtarget features //
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips Subtarget features //
//===---------------------------------------------------------------------===//
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
"Support 64-bit FP registers.">;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">;
"true",
"Only supports single precision float">;
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
"Enable o32 ABI">;
def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
@ -58,16 +59,16 @@ def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
"Mips1 ISA Support">;
def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
"Mips2 ISA Support">;
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support",
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion",
"Mips32", "Mips32 ISA Support",
[FeatureCondMov, FeatureBitCount]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg]>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips processors supported.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, MipsGenericItineraries, Features>;

31
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -1,16 +1,16 @@
//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer -------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
// of machine-dependent LLVM code to GAS-format MIPS assembly language.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-asm-printer"
#include "Mips.h"
@ -68,7 +68,8 @@ namespace {
const char *getCurrentABIString() const;
void emitFrameDirective();
void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
void printInstruction(const MachineInstr *MI,
raw_ostream &O); // autogen'd.
void EmitInstruction(const MachineInstr *MI) {
SmallString<128> Str;
raw_svector_ostream OS(Str);
@ -77,7 +78,8 @@ namespace {
}
virtual void EmitFunctionBodyStart();
virtual void EmitFunctionBodyEnd();
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock
*MBB) const;
static const char *getRegisterName(unsigned RegNo);
virtual void EmitFunctionEntryLabel();
@ -87,7 +89,7 @@ namespace {
#include "MipsGenAsmWriter.inc"
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// Mips Asm Directives
//
@ -116,11 +118,11 @@ namespace {
// stack pointer subtration, the first register in the mask (RA) will be
// saved at address 48-8=40.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mask directives
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Create a bitmask with all callee saved registers for CPU or Floating Point
// registers. For CPU registers consider RA, GP and FP for saving if necessary.
@ -172,9 +174,9 @@ void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Frame and Set directives
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// Frame Directive
void MipsAsmPrinter::emitFrameDirective() {
@ -236,8 +238,8 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
/// isBlockOnlyReachableByFallthough - Return true if the basic block has
/// exactly one predecessor and the control transfer mechanism between
/// the predecessor and this block is a fall-through.
bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
const {
bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock
*MBB) const {
// The predecessor has to be immediately before this block.
const MachineBasicBlock *Pred = *MBB->pred_begin();
@ -390,7 +392,8 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// FIXME: Use SwitchSection.
// Tell the assembler which ABI we are using
OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
OutStreamer.EmitRawText("\t.section .mdebug." +
Twine(getCurrentABIString()));
// TODO: handle O64 ABI
if (Subtarget->isABI_EABI()) {

18
lib/Target/Mips/MipsCallingConv.td
View File

@ -1,21 +1,21 @@
//===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===//
//===- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// This describes the calling conventions for Mips architecture.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// CCIfSubtarget - Match if the current subtarget has a feature F.
class CCIfSubtarget<string F, CCAction A>:
CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips O32 Calling Convention
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Only the return rules are defined here for O32. The rules for argument
// passing are defined in MipsISelLowering.cpp.
@ -30,9 +30,9 @@ def RetCC_MipsO32 : CallingConv<[
CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
]>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips EABI Calling Convention
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def CC_MipsEABI : CallingConv<[
// Promote i8/i16 arguments to i32.
@ -72,9 +72,9 @@ def RetCC_MipsEABI : CallingConv<[
CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
]>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips Calling Convention Dispatch
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def CC_Mips : CallingConv<[
CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>

4
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -5,11 +5,11 @@
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// Simple pass to fills delay slots with NOPs.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "delay-slot-filler"

18
lib/Target/Mips/MipsExpandPseudo.cpp
View File

@ -1,16 +1,16 @@
//===-- MipsExpandPseudo.cpp - Expand pseudo instructions ---------------------===//
//===-- MipsExpandPseudo.cpp - Expand pseudo instructions ---------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This pass expands pseudo instructions into target instructions after register
// allocation but before post-RA scheduling.
// This pass expands pseudo instructions into target instructions after
// register allocation but before post-RA scheduling.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-expand-pseudo"
@ -42,7 +42,8 @@ namespace {
private:
void ExpandBuildPairF64(MachineBasicBlock&, MachineBasicBlock::iterator);
void ExpandExtractElementF64(MachineBasicBlock&, MachineBasicBlock::iterator);
void ExpandExtractElementF64(MachineBasicBlock&,
MachineBasicBlock::iterator);
};
char MipsExpandPseudo::ID = 0;
} // end of anonymous namespace
@ -85,7 +86,8 @@ bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) {
void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
MachineBasicBlock::iterator I) {
unsigned DstReg = I->getOperand(0).getReg();
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
unsigned LoReg = I->getOperand(1).getReg();
unsigned HiReg = I->getOperand(2).getReg();
const TargetInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
DebugLoc dl = I->getDebugLoc();
const unsigned* SubReg =
@ -98,7 +100,7 @@ void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
}
void MipsExpandPseudo::ExpandExtractElementF64(MachineBasicBlock& MBB,
MachineBasicBlock::iterator I) {
MachineBasicBlock::iterator I) {
unsigned DstReg = I->getOperand(0).getReg();
unsigned SrcReg = I->getOperand(1).getReg();
unsigned N = I->getOperand(2).getImm();

28
lib/Target/Mips/MipsFrameLowering.cpp
View File

@ -1,15 +1,15 @@
//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
//=======- MipsFrameLowering.cpp - Mips Frame Information -----*- C++ -*-====//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the Mips implementation of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsFrameLowering.h"
#include "MipsInstrInfo.h"
@ -27,7 +27,7 @@
using namespace llvm;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// Stack Frame Processing methods
// +----------------------------+
@ -77,11 +77,11 @@ using namespace llvm;
// possible to detect those references and the offsets are adjusted to
// their real location.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// hasFP - Return true if the specified function should have a dedicated frame
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
// pointer register. This is true if the function has variable sized allocas
// or if frame pointer elimination is disabled.
bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
@ -203,9 +203,8 @@ void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
}
// expand pair of register and immediate if the immediate doesn't fit in the 16-bit
// offset field.
// expand pair of register and immediate if the immediate doesn't fit in the
// 16-bit offset field.
// e.g.
// if OrigImm = 0x10000, OrigReg = $sp:
// generate the following sequence of instrs:
@ -216,7 +215,8 @@ void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
// return true
static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
unsigned& NewReg, int& NewImm,
MachineBasicBlock& MBB, MachineBasicBlock::iterator I) {
MachineBasicBlock& MBB,
MachineBasicBlock::iterator I) {
// OrigImm fits in the 16-bit field
if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
NewReg = OrigReg;
@ -228,12 +228,14 @@ static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
DebugLoc DL = I->getDebugLoc();
int ImmLo = OrigImm & 0xffff;
int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + ((OrigImm & 0x8000) != 0);
int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
((OrigImm & 0x8000) != 0);
// FIXME: change this when mips goes MC".
BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg).addReg(Mips::AT);
BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
.addReg(Mips::AT);
NewReg = Mips::AT;
NewImm = ImmLo;

6
lib/Target/Mips/MipsFrameLowering.h
View File

@ -1,15 +1,15 @@
//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*---===//
//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
//
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPS_FRAMEINFO_H
#define MIPS_FRAMEINFO_H

14
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -1,15 +1,15 @@
//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file defines an instruction selector for the MIPS target.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-isel"
#include "Mips.h"
@ -34,14 +34,14 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instruction Selector Implementation
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
// instructions for SelectionDAG operations.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
namespace {
class MipsDAGToDAGISel : public SelectionDAGISel {

91
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -1,16 +1,16 @@
//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation ----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file defines the interfaces that Mips uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-lower"
#include "MipsISelLowering.h"
@ -221,8 +221,8 @@ static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
// Transform this to a MADD only if ADDENode and ADDCNode are the only users
// of the values of MultNode, in which case MultNode will be removed in later
// phases.
// If there exist users other than ADDENode or ADDCNode, this function returns
// here, which will result in MultNode being mapped to a single MULT
// If there exist users other than ADDENode or ADDCNode, this function
// returns here, which will result in MultNode being mapped to a single MULT
// instruction node rather than a pair of MULT and MADD instructions being
// produced.
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
@ -295,8 +295,8 @@ static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
// Transform this to a MSUB only if SUBENode and SUBCNode are the only users
// of the values of MultNode, in which case MultNode will be removed in later
// phases.
// If there exist users other than SUBENode or SUBCNode, this function returns
// here, which will result in MultNode being mapped to a single MULT
// If there exist users other than SUBENode or SUBCNode, this function
// returns here, which will result in MultNode being mapped to a single MULT
// instruction node rather than a pair of MULT and MSUB instructions being
// produced.
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
@ -444,8 +444,8 @@ static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
SDValue RHS = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc();
// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of node
// if necessary.
// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
// node if necessary.
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
@ -520,9 +520,9 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
return SDValue();
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Lower helper functions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// AddLiveIn - This helper function adds the specified physical register to the
// MachineFunction as a live in value. It also creates a corresponding
@ -653,9 +653,9 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
return BB;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Misc Lower Operation implementation
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
SDValue MipsTargetLowering::
LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
@ -851,7 +851,8 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
MachinePointerInfo(),
false, false, 0);
SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
MipsII::MO_ABS_LO);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
@ -879,9 +880,11 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
N->getOffset(), MipsII::MO_ABS_HI);
N->getOffset(),
MipsII::MO_ABS_HI);
SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
N->getOffset(), MipsII::MO_ABS_LO);
N->getOffset(),
MipsII::MO_ABS_LO);
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
@ -892,7 +895,8 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
CP, MachinePointerInfo::getConstantPool(),
false, false, 0);
SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
N->getOffset(), MipsII::MO_ABS_LO);
N->getOffset(),
MipsII::MO_ABS_LO);
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
}
@ -916,13 +920,13 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
false, false, 0);
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsGenCallingConv.inc"
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// TODO: Implement a generic logic using tblgen that can support this.
// Mips O32 ABI rules:
// ---
@ -933,7 +937,7 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
// not used, it must be shadowed. If only A3 is avaiable, shadow it and
// go to stack.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
@ -957,7 +961,8 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
// This must be the first arg of the call if no regs have been allocated.
// Initialize IntRegUsed in that case.
if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] ==
Mips::F12 &&
F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
IntRegUsed = false;
@ -1070,9 +1075,9 @@ static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
return false; // CC must always match
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Call Calling Convention Implementation
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// LowerCall - functions arguments are copied from virtual regs to
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
@ -1134,10 +1139,11 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, Arg,
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl,
MVT::i32, Arg,
DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, Arg,
DAG.getConstant(1, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
Arg, DAG.getConstant(1, MVT::i32));
if (!Subtarget->isLittle())
std::swap(Lo, Hi);
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
@ -1342,20 +1348,21 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
return Chain;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Formal Arguments Calling Convention Implementation
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// LowerFormalArguments - transform physical registers into virtual registers
/// and generate load operations for arguments places on the stack.
SDValue
MipsTargetLowering::LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals)
const {
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
&Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
@ -1456,7 +1463,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
// be used on emitPrologue) to avoid mis-calc of the first stack
// offset on PEI::calculateFrameObjectOffsets.
unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() + ArgSize;
LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() +
ArgSize;
int FI = MFI->CreateFixedObject(ArgSize, 0, true);
MipsFI->recordLoadArgsFI(FI, -(4 +
(FirstStackArgLoc + VA.getLocMemOffset())));
@ -1545,9 +1553,9 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
return Chain;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Return Value Calling Convention Implementation
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
SDValue
MipsTargetLowering::LowerReturn(SDValue Chain,
@ -1572,7 +1580,8 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
for (unsigned i = 0; i != RVLocs.size(); ++i)
if (RVLocs[i].isRegLoc())
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
DAG.getMachineFunction().getRegInfo()
.addLiveOut(RVLocs[i].getLocReg());
}
SDValue Flag;
@ -1616,9 +1625,9 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
Chain, DAG.getRegister(Mips::RA, MVT::i32));
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips Inline Assembly Support
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.

15
lib/Target/Mips/MipsISelLowering.h
View File

@ -1,16 +1,16 @@
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
//===-- MipsISelLowering.h - Mips DAG Lowering Interface -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file defines the interfaces that Mips uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MipsISELLOWERING_H
#define MipsISELLOWERING_H
@ -71,9 +71,9 @@ namespace llvm {
};
}
//===--------------------------------------------------------------------===//
//===-------------------------------------------------------------------===//
// TargetLowering Implementation
//===--------------------------------------------------------------------===//
//===-------------------------------------------------------------------===//
class MipsTargetLowering : public TargetLowering {
public:
@ -148,8 +148,9 @@ namespace llvm {
// Inline asm support
ConstraintType getConstraintType(const std::string &Constraint) const;
/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
/// Examine constraint string and operand type and determine a weight
/// value. The operand object must already have been set up with the
/// operand type.
ConstraintWeight getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const;

50
lib/Target/Mips/MipsInstrFPU.td
View File

@ -1,17 +1,17 @@
//===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===//
//===- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the Mips implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Instructions
// ------------------------
// * 64bit fp:
@ -21,7 +21,7 @@
// * 32bit fp:
// - 16 even 32-bit registers - single and double (aliased)
// - 32 32-bit registers (within single-only mode)
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Compare and Branch
def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
@ -51,16 +51,16 @@ def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
let PrintMethod = "printFCCOperand" in
def condcode : Operand<i32>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Feature predicates.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instruction Class Templates
//
// A set of multiclasses is used to address the register usage.
@ -72,7 +72,7 @@ def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
// D64 - double precision in 32 64bit fp registers (In64BitMode)
//
// Only S32 and D32 are supported right now.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
multiclass FFR1_1<bits<6> funct, string asmstr>
{
@ -91,7 +91,8 @@ multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
!strconcat(asmstr, ".d $fd, $fs"),
[(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
[(set AFGR64:$fd, (FOp AFGR64:$fs))]>,
Requires<[In32BitMode]>;
}
class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
@ -113,9 +114,9 @@ multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
Requires<[In32BitMode]>;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Instructions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
let ft = 0 in {
defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
@ -199,8 +200,8 @@ let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
// LWC1 and SWC1 can always be emitted with odd registers.
def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
[(set FGR32:$ft, (load addr:$addr))]>;
def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
[(store FGR32:$ft, addr:$addr)]>;
def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr),
"swc1 $ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
/// Floating-point Aritmetic
defm FADD : FFR1_4<0x10, "add", fadd>;
@ -208,9 +209,9 @@ defm FDIV : FFR1_4<0x03, "div", fdiv>;
defm FMUL : FFR1_4<0x02, "mul", fmul>;
defm FSUB : FFR1_4<0x01, "sub", fsub>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Branch Codes
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch.
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
@ -229,9 +230,9 @@ def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Flag Conditions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
// They must be kept in synch.
def MIPS_FCOND_F : PatLeaf<(i32 0)>;
@ -265,8 +266,9 @@ let hasDelaySlot = 1, Defs=[FCR31] in {
// Conditional moves:
// These instructions are expanded in MipsISelLowering::EmitInstrWithCustomInserter
// if target does not have conditional move instructions.
// These instructions are expanded in
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
// conditional move instructions.
// flag:int, data:float
let usesCustomInserter = 1, Constraints = "$F = $dst" in
class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
@ -315,9 +317,9 @@ let Predicates = [In32BitMode] in {
def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Pseudo-Instructions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
"# MOVCCRToCCR", []>;
@ -338,9 +340,9 @@ def ExtractElementF64 :
[(set CPURegs:$dst,
(MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Patterns
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def fpimm0 : PatLeaf<(fpimm), [{
return N->isExactlyValue(+0.0);
}]>;

36
lib/Target/Mips/MipsInstrFormats.td
View File

@ -1,13 +1,13 @@
//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
//===- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Describe MIPS instructions format
//
// CPU INSTRUCTION FORMATS
@ -19,7 +19,7 @@
// shamt - only used on shift instructions, contains the shift amount.
// funct - combined with opcode field give us an operation code.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Generic Mips Format
class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
@ -46,9 +46,9 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin>:
@ -70,9 +70,9 @@ class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
let Inst{5-0} = funct;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
@ -88,9 +88,9 @@ class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{15-0} = imm16;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Format J instruction class in Mips : <|opcode|address|>
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
@ -102,7 +102,7 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{25-0} = addr;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS
//
@ -113,11 +113,11 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
// fmt - double or single precision.
// funct - combined with opcode field give us an operation code.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
string asmstr, list<dag> pattern> :
@ -140,9 +140,9 @@ class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
let Inst{5-0} = funct;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
MipsInst<outs, ins, asmstr, pattern, NoItinerary>
@ -158,9 +158,9 @@ class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
let Inst{15-0} = imm16;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
MipsInst<outs, ins, asmstr, pattern, NoItinerary>

19
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -1,15 +1,15 @@
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
//===- MipsInstrInfo.cpp - Mips Instruction Information --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the Mips implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsInstrInfo.h"
#include "MipsTargetMachine.h"
@ -161,10 +161,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (RC == Mips::CPURegsRegisterClass)
BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
.addImm(0).addFrameIndex(FI);
else if (RC == Mips::FGR32RegisterClass)
BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
BuildMI(MBB, I, DL, get(Mips::SWC1))
.addReg(SrcReg, getKillRegState(isKill)).addImm(0).addFrameIndex(FI);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::SDC1))
@ -200,7 +200,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg)
.addImm(0).addFrameIndex(FI);
} else {
const TargetRegisterInfo *TRI =
MBB.getParent()->getTarget().getRegisterInfo();
@ -214,9 +215,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
llvm_unreachable("Register class not handled!");
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Branch Analysis
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
static unsigned GetAnalyzableBrOpc(unsigned Opc) {
return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||

11
lib/Target/Mips/MipsInstrInfo.h
View File

@ -1,15 +1,15 @@
//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
//===- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the Mips implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPSINSTRUCTIONINFO_H
#define MIPSINSTRUCTIONINFO_H
@ -124,7 +124,7 @@ namespace Mips {
namespace MipsII {
/// Target Operand Flag enum.
enum TOF {
//===------------------------------------------------------------------===//
//===-----------------------------------------------------------------===//
// Mips Specific MachineOperand flags.
MO_NO_FLAG,
@ -200,7 +200,8 @@ public:
bool KillSrc) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
unsigned SrcReg, bool isKill,
int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;

58
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1,27 +1,28 @@
//===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
//===- MipsInstrInfo.td - Mips Register defs --------------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
include "MipsInstrFormats.td"
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips profiles and nodes
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
SDTCisInt<4>]>;
SDTCisSameAs<1, 2>,
SDTCisSameAs<3, 4>,
SDTCisInt<4>]>;
def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
@ -70,9 +71,9 @@ def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
[SDNPOutGlue]>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
def HasSwap : Predicate<"Subtarget.hasSwap()">;
@ -80,9 +81,9 @@ def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
def IsMips32 : Predicate<"Subtarget.isMips32()">;
def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instruction operand types
def brtarget : Operand<OtherVT>;
@ -135,9 +136,9 @@ def immZExt5 : PatLeaf<(imm), [{
// since load and store instructions from stack used it.
def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Arithmetic 3 register operands
let isCommutable = 1 in
@ -337,9 +338,9 @@ class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
[], NoItinerary>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Pseudo instructions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// As stack alignment is always done with addiu, we need a 16-bit immediate
let Defs = [SP], Uses = [SP] in {
@ -368,15 +369,16 @@ def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
// are used, we have the same behavior, but get also a bunch of warnings
// from the assembler.
def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc),
".cprestore\t$loc\n", []>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// MipsI Instructions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
@ -491,8 +493,9 @@ def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
// Conditional moves:
// These instructions are expanded in MipsISelLowering::EmitInstrWithCustomInserter
// if target does not have conditional move instructions.
// These instructions are expanded in
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
// conditional move instructions.
// flag:int, data:int
let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in
class CondMovIntInt<bits<6> funct, string instr_asm> :
@ -523,9 +526,9 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
// it is a real instruction.
def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Small immediates
def : Pat<(i32 immSExt16:$in),
@ -674,9 +677,8 @@ def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
(XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Floating Point Support
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
include "MipsInstrFPU.td"

6
lib/Target/Mips/MipsMCAsmInfo.cpp
View File

@ -1,15 +1,15 @@
//===-- MipsMCAsmInfo.cpp - Mips asm properties ---------------------------===//
//===-- MipsMCAsmInfo.cpp - Mips asm properties --------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the declarations of the MipsMCAsmInfo properties.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsMCAsmInfo.h"
using namespace llvm;

6
lib/Target/Mips/MipsMCAsmInfo.h
View File

@ -1,15 +1,15 @@
//=====-- MipsMCAsmInfo.h - Mips asm properties ---------------*- C++ -*--====//
//=====-- MipsMCAsmInfo.h - Mips asm properties --------------*- C++ -*--====//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the declaration of the MipsMCAsmInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPSTARGETASMINFO_H
#define MIPSTARGETASMINFO_H

6
lib/Target/Mips/MipsMachineFunction.h
View File

@ -1,15 +1,15 @@
//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
//===-- MipsMachineFunctionInfo.h - Private data used for Mips ---*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file declares the Mips specific subclass of MachineFunctionInfo.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPS_MACHINE_FUNCTION_INFO_H
#define MIPS_MACHINE_FUNCTION_INFO_H

16
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -1,15 +1,15 @@
//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
//===- MipsRegisterInfo.cpp - MIPS Register Information -== ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the MIPS implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-reg-info"
@ -88,9 +88,9 @@ getRegisterNumbering(unsigned RegEnum)
unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Callee Saved Registers methods
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
/// Mips Callee Saved Registers
const unsigned* MipsRegisterInfo::
@ -196,12 +196,14 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
DebugLoc DL = II->getDebugLoc();
int ImmLo = OrigImm & 0xffff;
int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + ((OrigImm & 0x8000) != 0);
int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
((OrigImm & 0x8000) != 0);
// FIXME: change this when mips goes MC".
BuildMI(MBB, II, DL, TII->get(Mips::NOAT));
BuildMI(MBB, II, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
BuildMI(MBB, II, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg).addReg(Mips::AT);
BuildMI(MBB, II, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
.addReg(Mips::AT);
NewReg = Mips::AT;
NewImm = ImmLo;

6
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -1,15 +1,15 @@
//===- MipsRegisterInfo.h - Mips Register Information Impl ------*- C++ -*-===//
//===- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the Mips implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPSREGISTERINFO_H
#define MIPSREGISTERINFO_H

16
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -1,15 +1,15 @@
//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===//
//===- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Declarations that describe the MIPS register file
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// We have banks of 32 registers each.
class MipsReg<string n> : Register<n> {
@ -44,9 +44,9 @@ class AFPR<bits<5> num, string n, list<Register> subregs>
let SubRegIndices = [sub_fpeven, sub_fpodd];
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
let Namespace = "Mips" in {
@ -145,9 +145,9 @@ let Namespace = "Mips" in {
def FCR31 : Register<"31">;
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Register Classes
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def CPURegs : RegisterClass<"Mips", [i32], 32,
// Return Values and Arguments

16
lib/Target/Mips/MipsSchedule.td
View File

@ -1,21 +1,21 @@
//===- MipsSchedule.td - Mips Scheduling Definitions -------*- tablegen -*-===//
//===- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Functional units across Mips chips sets. Based on GCC/Mips backend files.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def ALU : FuncUnit;
def IMULDIV : FuncUnit;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Instruction Itinerary classes used for Mips
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def IIAlu : InstrItinClass;
def IILoad : InstrItinClass;
def IIStore : InstrItinClass;
@ -37,9 +37,9 @@ def IIFsqrtDouble : InstrItinClass;
def IIFrecipFsqrtStep : InstrItinClass;
def IIPseudo : InstrItinClass;
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Mips Generic instruction itineraries.
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,

6
lib/Target/Mips/MipsSelectionDAGInfo.cpp
View File

@ -1,15 +1,15 @@
//===-- MipsSelectionDAGInfo.cpp - Mips SelectionDAG Info -----------------===//
//===-- MipsSelectionDAGInfo.cpp - Mips SelectionDAG Info ----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file implements the MipsSelectionDAGInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#define DEBUG_TYPE "mips-selectiondag-info"
#include "MipsTargetMachine.h"

6
lib/Target/Mips/MipsSelectionDAGInfo.h
View File

@ -1,15 +1,15 @@
//===-- MipsSelectionDAGInfo.h - Mips SelectionDAG Info ---------*- C++ -*-===//
//===-- MipsSelectionDAGInfo.h - Mips SelectionDAG Info --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file defines the Mips subclass for TargetSelectionDAGInfo.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPSSELECTIONDAGINFO_H
#define MIPSSELECTIONDAGINFO_H

6
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -1,15 +1,15 @@
//===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===//
//===- MipsSubtarget.cpp - Mips Subtarget Information ----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file implements the Mips specific subclass of TargetSubtarget.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsSubtarget.h"
#include "Mips.h"

6
lib/Target/Mips/MipsSubtarget.h
View File

@ -1,15 +1,15 @@
//=====-- MipsSubtarget.h - Define Subtarget for the Mips -----*- C++ -*--====//
//=====-- MipsSubtarget.h - Define Subtarget for the Mips ----*- C++ -*--====//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file declares the Mips specific subclass of TargetSubtarget.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPSSUBTARGET_H
#define MIPSSUBTARGET_H

10
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -1,15 +1,15 @@
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips ------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// Implements the info about Mips target spec.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "Mips.h"
#include "MipsMCAsmInfo.h"
@ -34,8 +34,8 @@ extern "C" void LLVMInitializeMipsTarget() {
// an easier handling.
// Using CodeModel::Large enables different CALL behavior.
MipsTargetMachine::
MipsTargetMachine(const Target &T, const std::string &TT, const std::string &FS,
bool isLittle=false):
MipsTargetMachine(const Target &T, const std::string &TT,
const std::string &FS, bool isLittle=false) :
LLVMTargetMachine(T, TT),
Subtarget(TT, FS, isLittle),
DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") :

6
lib/Target/Mips/MipsTargetMachine.h
View File

@ -1,15 +1,15 @@
//===-- MipsTargetMachine.h - Define TargetMachine for Mips -00--*- C++ -*-===//
//===-- MipsTargetMachine.h - Define TargetMachine for Mips -00-*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file declares the Mips specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef MIPSTARGETMACHINE_H
#define MIPSTARGETMACHINE_H

10
lib/Target/Mips/MipsTargetObjectFile.cpp
View File

@ -1,11 +1,11 @@
//===-- MipsTargetObjectFile.cpp - Mips object files ----------------------===//
//===-- MipsTargetObjectFile.cpp - Mips object files ---------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsTargetObjectFile.h"
#include "MipsSubtarget.h"
@ -47,7 +47,8 @@ static bool IsInSmallSection(uint64_t Size) {
}
bool MipsTargetObjectFile::IsGlobalInSmallSection(const GlobalValue *GV,
const TargetMachine &TM) const {
const TargetMachine &TM)
const {
if (GV->isDeclaration() || GV->hasAvailableExternallyLinkage())
return false;
@ -98,5 +99,6 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
return SmallDataSection;
// Otherwise, we work the same as ELF.
return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang,TM);
return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang,
TM);
}

7
lib/Target/Mips/MipsTargetObjectFile.h
View File

@ -1,11 +1,11 @@
//===-- llvm/Target/MipsTargetObjectFile.h - Mips Object Info ---*- C++ -*-===//
//===-- llvm/Target/MipsTargetObjectFile.h - Mips Object Info --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#ifndef LLVM_TARGET_MIPS_TARGETOBJECTFILE_H
#define LLVM_TARGET_MIPS_TARGETOBJECTFILE_H
@ -25,7 +25,8 @@ namespace llvm {
/// IsGlobalInSmallSection - Return true if this global address should be
/// placed into small data/bss section.
bool IsGlobalInSmallSection(const GlobalValue *GV,
const TargetMachine &TM, SectionKind Kind)const;
const TargetMachine &TM,
SectionKind Kind) const;
bool IsGlobalInSmallSection(const GlobalValue *GV,
const TargetMachine &TM) const;