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Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2011-04-15 21:00:26 +00:00
parent b485de5d8c
commit 0bf3dfbef6
32 changed files with 299 additions and 270 deletions
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19
lib/Target/Mips/MipsInstrInfo.cpp
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@@ -1,15 +1,15 @@
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
//===- MipsInstrInfo.cpp - Mips Instruction Information --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
//
// This file contains the Mips implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
#include "MipsInstrInfo.h"
#include "MipsTargetMachine.h"
@@ -161,10 +161,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (RC == Mips::CPURegsRegisterClass)
BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
.addImm(0).addFrameIndex(FI);
else if (RC == Mips::FGR32RegisterClass)
BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
.addImm(0).addFrameIndex(FI);
BuildMI(MBB, I, DL, get(Mips::SWC1))
.addReg(SrcReg, getKillRegState(isKill)).addImm(0).addFrameIndex(FI);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::SDC1))
@@ -200,7 +200,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
else if (RC == Mips::AFGR64RegisterClass) {
if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg)
.addImm(0).addFrameIndex(FI);
} else {
const TargetRegisterInfo *TRI =
MBB.getParent()->getTarget().getRegisterInfo();
@@ -214,9 +215,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
llvm_unreachable("Register class not handled!");
}
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
// Branch Analysis
//===----------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
static unsigned GetAnalyzableBrOpc(unsigned Opc) {
return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||