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[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -170,6 +170,7 @@ def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
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}
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let DecoderNamespace = "Mips64" in
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def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
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def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
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def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
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let DecoderNamespace = "Mips64" in {
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@ -329,6 +330,8 @@ def : InstAlias<"not $rt, $rs",
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(NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
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def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
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Requires<[HasMips64]>;
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def : InstAlias<"daddu $rs, $rt, $imm",
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(DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
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1>;
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@ -367,6 +367,7 @@ class LUI_FM {
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}
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class JALR_FM {
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bits<5> rd;
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bits<5> rs;
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bits<32> Inst;
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@ -374,7 +375,7 @@ class JALR_FM {
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-16} = 0;
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let Inst{15-11} = 31;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = 9;
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}
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@ -565,9 +565,14 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in {
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let DecoderMethod = "DecodeJumpTarget";
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}
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class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
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Register RetReg>:
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PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
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PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
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class JumpLinkReg<string opstr, RegisterClass RC>:
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InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"),
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[(MipsJmpLink RC:$rs)], IIBranch, FrmR>;
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InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
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[], IIBranch, FrmR>;
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class BGEZAL_FT<string opstr, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, brtarget:$offset),
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@ -865,6 +870,7 @@ def BAL_BR: BAL_FT, BAL_FM;
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def JAL : JumpLink<"jal">, FJ<3>;
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def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
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def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
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def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
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def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
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def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
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@ -972,6 +978,7 @@ def : InstAlias<"and $rs, $rt, $imm",
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(ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
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Requires<[NotMips64]>;
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def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
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def : InstAlias<"not $rt, $rs",
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(NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
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def : InstAlias<"neg $rt, $rs",
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@ -56,6 +56,10 @@ end_of_code:
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
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@ -67,6 +71,10 @@ end_of_code:
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nop
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jalr $6
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nop
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jalr $31, $25
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nop
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jalr $10, $11
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nop
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jr $7
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nop
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j $7
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