mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-18 13:34:04 +00:00
R600/SI: cleanup VGPR encoding
Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174656 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
60fc58262f
commit
184f5c1545
@ -127,7 +127,7 @@ void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
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} else {
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assert(!"Unknown register class");
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}
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hwReg = RI->getEncodingValue(reg);
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hwReg = RI->getEncodingValue(reg) & 0xff;
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maxUsed = hwReg + width - 1;
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if (isSGPR) {
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MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
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@ -24,35 +24,6 @@
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
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#define SI_INSTR_FLAGS_ENCODING_MASK 0xf
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// These must be kept in sync with SIInstructions.td and also the
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// InstrEncodingInfo array in SIInstrInfo.cpp.
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//
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// NOTE: This enum is only used to identify the encoding type within LLVM,
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// the actual encoding type that is part of the instruction format is different
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namespace SIInstrEncodingType {
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enum Encoding {
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EXP = 0,
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LDS = 1,
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MIMG = 2,
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MTBUF = 3,
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MUBUF = 4,
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SMRD = 5,
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SOP1 = 6,
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SOP2 = 7,
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SOPC = 8,
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SOPK = 9,
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SOPP = 10,
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VINTRP = 11,
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VOP1 = 12,
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VOP2 = 13,
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VOP3 = 14,
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VOPC = 15
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};
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}
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using namespace llvm;
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namespace {
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@ -91,25 +62,6 @@ public:
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/// \brief Encoding for when 4 consectuive registers are used
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virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const;
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/// \brief Post-Encoder method for VOP instructions
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virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
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private:
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/// \returns this SIInstrEncodingType for this instruction.
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unsigned getEncodingType(const MCInst &MI) const;
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/// \brief Get then size in bytes of this instructions encoding.
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unsigned getEncodingBytes(const MCInst &MI) const;
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/// \returns the hardware encoding for a register
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unsigned getRegBinaryCode(unsigned reg) const;
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/// \brief Generated function that returns the hardware encoding for
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/// a register
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unsigned getHWRegNum(unsigned reg) const;
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};
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} // End anonymous namespace
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@ -124,7 +76,7 @@ MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
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void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
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unsigned bytes = getEncodingBytes(MI);
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unsigned bytes = MCII.get(MI.getOpcode()).getSize();
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for (unsigned i = 0; i < bytes; i++) {
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OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
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}
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@ -134,7 +86,7 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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return getRegBinaryCode(MO.getReg());
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return MRI.getEncodingValue(MO.getReg());
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} else if (MO.isImm()) {
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return MO.getImm();
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} else if (MO.isFPImm()) {
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@ -163,9 +115,8 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
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unsigned shift) const {
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unsigned regCode = getRegBinaryCode(MI.getOperand(OpNo).getReg());
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return regCode >> shift;
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return 0;
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unsigned regCode = MRI.getEncodingValue(MI.getOperand(OpNo).getReg());
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return (regCode & 0xff) >> shift;
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}
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unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
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unsigned OpNo ,
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@ -178,87 +129,3 @@ unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixup) const {
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return GPRAlign(MI, OpNo, 2);
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}
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//===----------------------------------------------------------------------===//
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// Post Encoder Callbacks
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//===----------------------------------------------------------------------===//
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uint64_t SIMCCodeEmitter::VOPPostEncode(const MCInst &MI, uint64_t Value) const{
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unsigned encodingType = getEncodingType(MI);
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unsigned numSrcOps;
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unsigned vgprBitOffset;
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if (encodingType == SIInstrEncodingType::VOP3) {
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numSrcOps = 3;
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vgprBitOffset = 32;
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} else {
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numSrcOps = 1;
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vgprBitOffset = 0;
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}
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// Add one to skip over the destination reg operand.
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for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
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const MCOperand &MO = MI.getOperand(opIdx);
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if (MO.isReg()) {
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unsigned reg = MI.getOperand(opIdx).getReg();
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if (AMDGPUMCRegisterClasses[AMDGPU::VReg_32RegClassID].contains(reg) ||
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AMDGPUMCRegisterClasses[AMDGPU::VReg_64RegClassID].contains(reg)) {
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Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
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}
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} else if (MO.isFPImm()) {
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union {
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float f;
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uint32_t i;
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} Imm;
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// XXX: Not all instructions can use inline literals
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// XXX: We should make sure this is a 32-bit constant
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Imm.f = MO.getFPImm();
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Value |= ((uint64_t)Imm.i) << 32;
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}
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}
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return Value;
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}
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//===----------------------------------------------------------------------===//
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// Encoding helper functions
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//===----------------------------------------------------------------------===//
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unsigned SIMCCodeEmitter::getEncodingType(const MCInst &MI) const {
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return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
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}
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unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
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// These instructions aren't real instructions with an encoding type, so
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// we need to manually specify their size.
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switch (MI.getOpcode()) {
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default: break;
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case AMDGPU::SI_LOAD_LITERAL_I32:
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case AMDGPU::SI_LOAD_LITERAL_F32:
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return 4;
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}
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unsigned encoding_type = getEncodingType(MI);
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switch (encoding_type) {
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case SIInstrEncodingType::EXP:
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case SIInstrEncodingType::LDS:
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case SIInstrEncodingType::MUBUF:
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case SIInstrEncodingType::MTBUF:
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case SIInstrEncodingType::MIMG:
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case SIInstrEncodingType::VOP3:
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return 8;
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default:
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return 4;
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}
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}
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unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
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switch (reg) {
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case AMDGPU::M0: return 124;
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case AMDGPU::SREG_LIT_0: return 128;
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case AMDGPU::SI_LITERAL_CONSTANT: return 255;
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default: return MRI.getEncodingValue(reg);
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}
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}
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@ -35,12 +35,6 @@ public:
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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/// \returns the encoding type of this instruction.
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unsigned getEncodingType(const MachineInstr &MI) const;
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/// \returns the size of this instructions encoding in number of bytes.
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unsigned getEncodingBytes(const MachineInstr &MI) const;
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virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const;
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@ -81,9 +75,9 @@ public:
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 4,
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EXP_CNT = 1 << 5,
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LGKM_CNT = 1 << 6
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VM_CNT = 1 << 0,
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EXP_CNT = 1 << 1,
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LGKM_CNT = 1 << 2
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};
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}
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@ -70,27 +70,27 @@ def IMM12bit : ImmLeaf <
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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AMDGPUInst<outs, ins, asm, pattern> {
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field bits<4> EncodingType = 0;
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field bits<1> VM_CNT = 0;
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field bits<1> EXP_CNT = 0;
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field bits<1> LGKM_CNT = 0;
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let TSFlags{3-0} = EncodingType;
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let TSFlags{4} = VM_CNT;
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let TSFlags{5} = EXP_CNT;
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let TSFlags{6} = LGKM_CNT;
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let TSFlags{0} = VM_CNT;
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let TSFlags{1} = EXP_CNT;
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let TSFlags{2} = LGKM_CNT;
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}
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class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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field bits<32> Inst;
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let Size = 4;
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}
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class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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field bits<64> Inst;
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let Size = 8;
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}
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class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
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@ -137,7 +137,6 @@ def EXP : Enc64<
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let Inst{47-40} = VSRC1;
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let Inst{55-48} = VSRC2;
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let Inst{63-56} = VSRC3;
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let EncodingType = 0; //SIInstrEncodingType::EXP
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let EXP_CNT = 1;
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}
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@ -172,7 +171,6 @@ class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{47-40} = VDATA;
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let Inst{52-48} = SRSRC;
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let Inst{57-53} = SSAMP;
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let EncodingType = 2; //SIInstrEncodingType::MIMG
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let VM_CNT = 1;
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let EXP_CNT = 1;
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@ -210,7 +208,6 @@ class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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let EncodingType = 3; //SIInstrEncodingType::MTBUF
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let VM_CNT = 1;
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let EXP_CNT = 1;
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@ -248,7 +245,6 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{54} = SLC;
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let Inst{55} = TFE;
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let Inst{63-56} = SOFFSET;
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let EncodingType = 4; //SIInstrEncodingType::MUBUF
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let VM_CNT = 1;
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let EXP_CNT = 1;
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@ -271,7 +267,6 @@ class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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let Inst{21-15} = SDST;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let EncodingType = 5; //SIInstrEncodingType::SMRD
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let LGKM_CNT = 1;
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}
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@ -286,7 +281,6 @@ class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{15-8} = op;
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let Inst{22-16} = SDST;
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let Inst{31-23} = 0x17d; //encoding;
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let EncodingType = 6; //SIInstrEncodingType::SOP1
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let mayLoad = 0;
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let mayStore = 0;
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@ -305,7 +299,6 @@ class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{22-16} = SDST;
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let Inst{29-23} = op;
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let Inst{31-30} = 0x2; // encoding
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let EncodingType = 7; // SIInstrEncodingType::SOP2
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let mayLoad = 0;
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let mayStore = 0;
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@ -322,7 +315,6 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17e;
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let EncodingType = 8; // SIInstrEncodingType::SOPC
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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@ -340,7 +332,6 @@ class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{22-16} = SDST;
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let Inst{27-23} = op;
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let Inst{31-28} = 0xb; //encoding
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let EncodingType = 9; // SIInstrEncodingType::SOPK
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let mayLoad = 0;
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let mayStore = 0;
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@ -358,7 +349,6 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17f; // encoding
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let EncodingType = 10; // SIInstrEncodingType::SOPP
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let mayLoad = 0;
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let mayStore = 0;
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@ -381,7 +371,6 @@ class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{17-16} = op;
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let Inst{25-18} = VDST;
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let Inst{31-26} = 0x32; // encoding
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let EncodingType = 11; // SIInstrEncodingType::VINTRP
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let neverHasSideEffects = 1;
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let mayLoad = 1;
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@ -399,9 +388,6 @@ class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{24-17} = VDST;
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let Inst{31-25} = 0x3f; //encoding
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let EncodingType = 12; // SIInstrEncodingType::VOP1
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let PostEncoderMethod = "VOPPostEncode";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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@ -420,9 +406,6 @@ class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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let EncodingType = 13; // SIInstrEncodingType::VOP2
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let PostEncoderMethod = "VOPPostEncode";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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@ -451,9 +434,6 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{60-59} = OMOD;
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let Inst{63-61} = NEG;
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let EncodingType = 14; // SIInstrEncodingType::VOP3
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let PostEncoderMethod = "VOPPostEncode";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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@ -480,9 +460,6 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let Inst{60-59} = OMOD;
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let Inst{63-61} = NEG;
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let EncodingType = 14; // SIInstrEncodingType::VOP3
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let PostEncoderMethod = "VOPPostEncode";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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@ -499,8 +476,6 @@ class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
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let Inst{24-17} = op;
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let Inst{31-25} = 0x3e;
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let EncodingType = 15; //SIInstrEncodingType::VOPC
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let PostEncoderMethod = "VOPPostEncode";
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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let mayStore = 0;
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@ -12,7 +12,9 @@ class SI_64 <string n, list<Register> subregs, bits<16> encoding> : RegisterWith
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class SGPR_32 <bits<16> num, string name> : SIReg<name, num>;
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class VGPR_32 <bits<16> num, string name> : SIReg<name, num>;
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class VGPR_32 <bits<16> num, string name> : SIReg<name, num> {
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let HWEncoding{8} = 1;
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}
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// Special Registers
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def VCC : SIReg<"VCC", 106>;
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