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Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140181 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-09-20 21:38:18 +00:00
parent 1daa5bea58
commit 0d18174f0f
2 changed files with 43 additions and 9 deletions
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8
lib/Target/ARM/ARM.td
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@@ -108,7 +108,7 @@ def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
[HasV5TEOps]>;
def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
"Support ARM v6t2 instructions",
[HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
[HasV6Ops, FeatureThumb2]>;
def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
"Support ARM v7 instructions",
[HasV6T2Ops]>;
@@ -188,9 +188,11 @@ def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
FeatureDB]>;
// V6T2 Processors.
def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops]>;
def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
FeatureDSPThumb2]>;
def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
FeatureHasSlowFPVMLx]>;
FeatureHasSlowFPVMLx,
FeatureDSPThumb2]>;
// V7a Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,