mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
Reflects the chanegs made to PredicateOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
16b6598325
commit
0e1d37904a
@ -1192,6 +1192,7 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
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// L2:
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ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
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CC = ARMCC::getOppositeCondition(CC);
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unsigned CCReg = MI->getOperand(2).getReg();
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// If the branch is at the end of its MBB and that has a fall-through block,
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// direct the updated conditional branch to the fall-through block. Otherwise,
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@ -1241,7 +1242,8 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
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// Insert a new conditional branch and a new unconditional branch.
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// Also update the ImmBranch as well as adding a new entry for the new branch.
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BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB).addImm(CC);
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BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB)
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.addImm(CC).addReg(CCReg);
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Br.MI = &MBB->back();
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BBSizes[MBB->getNumber()] += ARM::GetInstSize(&MBB->back());
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BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
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@ -1127,8 +1127,9 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
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if (LHS.getValueType() == MVT::i32) {
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SDOperand ARMCC;
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SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
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return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
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return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
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}
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ARMCC::CondCodes CondCode, CondCode2;
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@ -1136,14 +1137,15 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
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std::swap(TrueVal, FalseVal);
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SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
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SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
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ARMCC, Cmp);
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ARMCC, CCR, Cmp);
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if (CondCode2 != ARMCC::AL) {
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SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
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// FIXME: Needs another CMP because flag can have but one use.
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SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
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Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
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Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
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}
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return Result;
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}
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@ -1158,8 +1160,9 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
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if (LHS.getValueType() == MVT::i32) {
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SDOperand ARMCC;
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SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
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return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
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return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
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}
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assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
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@ -1170,13 +1173,14 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
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SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
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SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
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SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
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SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
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SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
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SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
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if (CondCode2 != ARMCC::AL) {
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ARMCC = DAG.getConstant(CondCode2, MVT::i32);
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SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
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Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
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SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
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Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
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}
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return Res;
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}
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@ -1228,7 +1232,8 @@ static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
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SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
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SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
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SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
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return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
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SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
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}
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static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
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@ -1472,7 +1477,7 @@ ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
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.addImm(MI->getOperand(3).getImm());
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.addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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@ -322,6 +322,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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Cond.push_back(LastInst->getOperand(1));
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Cond.push_back(LastInst->getOperand(2));
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return false;
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}
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return true; // Can't handle indirect branch.
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@ -341,6 +342,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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(SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
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TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
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Cond.push_back(SecondLastInst->getOperand(1));
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Cond.push_back(SecondLastInst->getOperand(2));
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FBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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@ -397,19 +399,21 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"ARM branch conditions have two components!");
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch?
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BuildMI(&MBB, get(BOpc)).addMBB(TBB);
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else
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB).addImm(Cond[0].getImm());
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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return 1;
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}
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// Two-way conditional branch.
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB).addImm(Cond[0].getImm());
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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BuildMI(&MBB, get(BOpc)).addMBB(FBB);
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return 2;
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}
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@ -452,6 +456,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
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if (Opc == ARM::B || Opc == ARM::tB) {
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MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
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MI->addImmOperand(Pred[0].getImmedValue());
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MI->addRegOperand(Pred[1].getReg(), false);
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return true;
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}
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@ -459,6 +464,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
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if (PIdx != -1) {
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MachineOperand &PMO = MI->getOperand(PIdx);
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PMO.setImm(Pred[0].getImmedValue());
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MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
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return true;
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}
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return false;
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@ -467,7 +473,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
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bool
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ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
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const std::vector<MachineOperand> &Pred2) const{
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if (Pred1.size() > 1 || Pred2.size() > 1)
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if (Pred1.size() > 2 || Pred2.size() > 2)
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return false;
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ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
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@ -66,7 +66,8 @@ namespace {
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SmallVector<MachineBasicBlock::iterator, 4>
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MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
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int Opcode, unsigned Size, ARMCC::CondCodes Pred,
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int Opcode, unsigned Size,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned Scratch, MemOpQueue &MemOps);
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void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
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@ -112,7 +113,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
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/// It returns true if the transformation is done.
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static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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int Offset, unsigned Base, bool BaseKill, int Opcode,
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ARMCC::CondCodes Pred, unsigned Scratch,
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ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
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SmallVector<std::pair<unsigned, bool>, 8> &Regs,
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const TargetInstrInfo *TII) {
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// Only a single register to load / store. Don't bother.
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@ -156,7 +157,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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return false; // Probably not worth it then.
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BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
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.addReg(Base, false, false, BaseKill).addImm(ImmedOffset).addImm(Pred);
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.addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
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.addImm(Pred).addReg(PredReg);
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Base = NewBase;
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BaseKill = true; // New base is always killed right its use.
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}
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@ -166,10 +168,10 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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Opcode = getLoadStoreMultipleOpcode(Opcode);
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MachineInstrBuilder MIB = (isAM4)
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? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
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.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred)
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.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
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: BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
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.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
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.addImm(Pred);
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.addImm(Pred).addReg(PredReg);
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for (unsigned i = 0; i != NumRegs; ++i)
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MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second);
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@ -181,8 +183,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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SmallVector<MachineBasicBlock::iterator, 4>
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ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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unsigned Base, int Opcode, unsigned Size,
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ARMCC::CondCodes Pred, unsigned Scratch,
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MemOpQueue &MemOps) {
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned Scratch, MemOpQueue &MemOps) {
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SmallVector<MachineBasicBlock::iterator, 4> Merges;
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bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
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int Offset = MemOps[SIndex].Offset;
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@ -209,8 +211,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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PRegNum = RegNum;
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} else {
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// Can't merge this in. Try merge the earlier ones first.
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if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, Scratch,
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Regs, TII)) {
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if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg,
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Scratch, Regs, TII)) {
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Merges.push_back(prior(Loc));
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for (unsigned j = SIndex; j < i; ++j) {
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MBB.erase(MemOps[j].MBBI);
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@ -218,7 +220,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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}
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}
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SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
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MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, Scratch, MemOps);
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MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,MemOps);
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Merges.append(Merges2.begin(), Merges2.end());
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return Merges;
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}
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@ -230,8 +232,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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}
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bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
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if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, Scratch,
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Regs, TII)) {
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if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg,
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Scratch, Regs, TII)) {
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Merges.push_back(prior(Loc));
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for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
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MBB.erase(MemOps[i].MBBI);
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@ -243,29 +245,41 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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}
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/// getInstrPredicate - If instruction is predicated, returns its predicate
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/// condition, otherwise returns AL.
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static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI) {
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/// condition, otherwise returns AL. It also returns the condition code
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/// register by reference.
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static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
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int PIdx = MI->findFirstPredOperandIdx();
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return PIdx == -1 ? ARMCC::AL
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: (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
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if (PIdx == -1) {
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PredReg = 0;
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return ARMCC::AL;
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}
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PredReg = MI->getOperand(PIdx+1).getReg();
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return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
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}
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static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
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unsigned Bytes, ARMCC::CondCodes Pred) {
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unsigned Bytes, ARMCC::CondCodes Pred,
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unsigned PredReg) {
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unsigned MyPredReg = 0;
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return (MI && MI->getOpcode() == ARM::SUBri &&
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MI->getOperand(0).getReg() == Base &&
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MI->getOperand(1).getReg() == Base &&
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ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
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getInstrPredicate(MI) == Pred);
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getInstrPredicate(MI, MyPredReg) == Pred &&
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MyPredReg == PredReg);
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}
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static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
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unsigned Bytes, ARMCC::CondCodes Pred) {
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unsigned Bytes, ARMCC::CondCodes Pred,
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unsigned PredReg) {
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unsigned MyPredReg = 0;
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return (MI && MI->getOpcode() == ARM::ADDri &&
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MI->getOperand(0).getReg() == Base &&
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MI->getOperand(1).getReg() == Base &&
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ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
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getInstrPredicate(MI) == Pred);
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getInstrPredicate(MI, MyPredReg) == Pred &&
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MyPredReg == PredReg);
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}
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static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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@ -281,7 +295,7 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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return 8;
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case ARM::LDM:
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case ARM::STM:
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return (MI->getNumOperands() - 3) * 4;
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return (MI->getNumOperands() - 4) * 4;
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case ARM::FLDMS:
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case ARM::FSTMS:
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case ARM::FLDMD:
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@ -307,7 +321,8 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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MachineInstr *MI = MBBI;
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unsigned Base = MI->getOperand(0).getReg();
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unsigned Bytes = getLSMultipleTransferSize(MI);
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ARMCC::CondCodes Pred = getInstrPredicate(MI);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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int Opcode = MI->getOpcode();
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bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::STM;
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@ -326,12 +341,12 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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if (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
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if (Mode == ARM_AM::ia &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
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MBB.erase(PrevMBBI);
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return true;
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} else if (Mode == ARM_AM::ib &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
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MBB.erase(PrevMBBI);
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return true;
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@ -341,12 +356,12 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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if (MBBI != MBB.end()) {
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MachineBasicBlock::iterator NextMBBI = next(MBBI);
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if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
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isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
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isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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MBB.erase(NextMBBI);
|
||||
return true;
|
||||
} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
|
||||
isMatchingDecrement(NextMBBI, Base, Bytes, Pred)) {
|
||||
isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
|
||||
MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
|
||||
MBB.erase(NextMBBI);
|
||||
return true;
|
||||
@ -362,7 +377,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
|
||||
if (MBBI != MBB.begin()) {
|
||||
MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
|
||||
if (Mode == ARM_AM::ia &&
|
||||
isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
|
||||
isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
|
||||
MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
|
||||
MBB.erase(PrevMBBI);
|
||||
return true;
|
||||
@ -372,7 +387,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
|
||||
if (MBBI != MBB.end()) {
|
||||
MachineBasicBlock::iterator NextMBBI = next(MBBI);
|
||||
if (Mode == ARM_AM::ia &&
|
||||
isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
|
||||
isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
|
||||
MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
|
||||
MBB.erase(NextMBBI);
|
||||
}
|
||||
@ -430,17 +445,19 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
|
||||
if (isLd && MI->getOperand(0).getReg() == Base)
|
||||
return false;
|
||||
|
||||
ARMCC::CondCodes Pred = getInstrPredicate(MI);
|
||||
unsigned PredReg = 0;
|
||||
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
||||
bool DoMerge = false;
|
||||
ARM_AM::AddrOpc AddSub = ARM_AM::add;
|
||||
unsigned NewOpc = 0;
|
||||
if (MBBI != MBB.begin()) {
|
||||
MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
|
||||
if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
|
||||
if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
|
||||
DoMerge = true;
|
||||
AddSub = ARM_AM::sub;
|
||||
NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
|
||||
} else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes, Pred)) {
|
||||
} else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes,
|
||||
Pred, PredReg)) {
|
||||
DoMerge = true;
|
||||
NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
|
||||
}
|
||||
@ -450,11 +467,11 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
|
||||
|
||||
if (!DoMerge && MBBI != MBB.end()) {
|
||||
MachineBasicBlock::iterator NextMBBI = next(MBBI);
|
||||
if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred)) {
|
||||
if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
|
||||
DoMerge = true;
|
||||
AddSub = ARM_AM::sub;
|
||||
NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
|
||||
} else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
|
||||
} else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
|
||||
DoMerge = true;
|
||||
NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
|
||||
}
|
||||
@ -474,22 +491,24 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
|
||||
// LDR_PRE, LDR_POST;
|
||||
BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
|
||||
.addReg(Base, true)
|
||||
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred);
|
||||
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
|
||||
else
|
||||
// FLDMS, FLDMD
|
||||
BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
|
||||
.addImm(Offset).addImm(Pred).addReg(MI->getOperand(0).getReg(), true);
|
||||
.addImm(Offset).addImm(Pred).addReg(PredReg)
|
||||
.addReg(MI->getOperand(0).getReg(), true);
|
||||
} else {
|
||||
MachineOperand &MO = MI->getOperand(0);
|
||||
if (isAM2)
|
||||
// STR_PRE, STR_POST;
|
||||
BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
|
||||
.addReg(MO.getReg(), false, false, MO.isKill())
|
||||
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred);
|
||||
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
|
||||
else
|
||||
// FSTMS, FSTMD
|
||||
BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset)
|
||||
.addImm(Pred).addReg(MO.getReg(), false, false, MO.isKill());
|
||||
.addImm(Pred).addReg(PredReg)
|
||||
.addReg(MO.getReg(), false, false, MO.isKill());
|
||||
}
|
||||
MBB.erase(MBBI);
|
||||
|
||||
@ -541,6 +560,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
int CurrOpc = -1;
|
||||
unsigned CurrSize = 0;
|
||||
ARMCC::CondCodes CurrPred = ARMCC::AL;
|
||||
unsigned CurrPredReg = 0;
|
||||
unsigned Position = 0;
|
||||
|
||||
RS->enterBasicBlock(&MBB);
|
||||
@ -556,9 +576,10 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
|
||||
unsigned Size = getLSMultipleTransferSize(MBBI);
|
||||
unsigned Base = MBBI->getOperand(1).getReg();
|
||||
ARMCC::CondCodes Pred = getInstrPredicate(MBBI);
|
||||
unsigned PredReg = 0;
|
||||
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
|
||||
const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
|
||||
unsigned OffField = MBBI->getOperand(TID->numOperands-2).getImm();
|
||||
unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
|
||||
int Offset = isAM2
|
||||
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
|
||||
if (isAM2) {
|
||||
@ -584,6 +605,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
CurrOpc = Opcode;
|
||||
CurrSize = Size;
|
||||
CurrPred = Pred;
|
||||
CurrPredReg = PredReg;
|
||||
MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
|
||||
NumMemOps++;
|
||||
Advance = true;
|
||||
@ -594,6 +616,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
}
|
||||
|
||||
if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
|
||||
// No need to match PredReg.
|
||||
// Continue adding to the queue.
|
||||
if (Offset > MemOps.back().Offset) {
|
||||
MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
|
||||
@ -639,8 +662,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
|
||||
// Merge ops.
|
||||
SmallVector<MachineBasicBlock::iterator,4> MBBII =
|
||||
MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, CurrPred,
|
||||
Scratch, MemOps);
|
||||
MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize,
|
||||
CurrPred, CurrPredReg, Scratch, MemOps);
|
||||
|
||||
// Try folding preceeding/trailing base inc/dec into the generated
|
||||
// LDM/STM ops.
|
||||
@ -664,6 +687,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
||||
CurrOpc = -1;
|
||||
CurrSize = 0;
|
||||
CurrPred = ARMCC::AL;
|
||||
CurrPredReg = 0;
|
||||
if (NumMemOps) {
|
||||
MemOps.clear();
|
||||
NumMemOps = 0;
|
||||
|
Loading…
Reference in New Issue
Block a user